Simulation Results: chip

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.82 %
  • code
  • 83.92 %
  • assert
  • 97.49 %
  • func
  • 46.06 %
  • line
  • 93.99 %
  • branch
  • 92.41 %
  • cond
  • 87.60 %
  • toggle
  • 88.48 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
74.82%
V2S
100.00%
V3
65.38%
unmapped
54.55%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 167.220s 2853.117us 1 1 100.00
chip_sw_example_rom 72.150s 2540.332us 1 1 100.00
chip_sw_example_manufacturer 158.150s 2941.713us 1 1 100.00
chip_sw_example_concurrency 164.440s 3228.103us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 178.250s 4552.972us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 508.520s 6016.418us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 790.540s 8551.001us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4676.090s 32220.421us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 52.350s 2268.480us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4676.090s 32220.421us 1 1 100.00
chip_csr_rw 508.520s 6016.418us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.770s 245.558us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 329.520s 4088.065us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 329.520s 4088.065us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 329.520s 4088.065us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 336.790s 4020.414us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 336.790s 4020.414us 1 1 100.00
chip_sw_uart_tx_rx_idx1 377.780s 4318.813us 1 1 100.00
chip_sw_uart_tx_rx_idx2 352.810s 4620.745us 1 1 100.00
chip_sw_uart_tx_rx_idx3 392.110s 4402.888us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 948.660s 8549.599us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 377.080s 3890.885us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1043.520s 13615.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 156.010s 5403.335us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 156.010s 5403.335us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 164.930s 2875.444us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 168.910s 3265.791us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 202.500s 5100.169us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 881.910s 12791.078us 1 1 100.00
chip_tap_straps_testunlock0 494.060s 8262.145us 1 1 100.00
chip_tap_straps_rma 167.290s 3319.544us 1 1 100.00
chip_tap_straps_prod 1040.810s 15339.319us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 190.160s 3123.041us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 778.180s 8230.271us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 459.400s 5760.059us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 459.400s 5760.059us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 598.910s 8627.836us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 789.220s 9430.522us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 422.980s 4256.262us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 679.410s 6424.236us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3921.490s 18954.261us 1 1 100.00
chip_sw_aes_enc_jitter_en 189.850s 3286.858us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 671.330s 7298.236us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.240s 2833.382us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 870.730s 8542.815us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 157.620s 2530.032us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 393.810s 4648.711us 1 1 100.00
chip_sw_clkmgr_jitter 110.020s 2875.559us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 180.910s 2840.686us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 331.650s 5264.800us 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 260.590s 5203.356us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 185.620s 3165.426us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 260.590s 5203.356us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 164.440s 3574.321us 1 1 100.00
chip_sw_aes_smoketest 168.520s 2894.223us 1 1 100.00
chip_sw_aon_timer_smoketest 193.370s 3292.361us 1 1 100.00
chip_sw_clkmgr_smoketest 160.110s 3459.780us 1 1 100.00
chip_sw_csrng_smoketest 172.370s 3104.069us 1 1 100.00
chip_sw_entropy_src_smoketest 987.720s 7244.744us 1 1 100.00
chip_sw_gpio_smoketest 165.890s 3069.375us 1 1 100.00
chip_sw_hmac_smoketest 206.830s 3539.827us 1 1 100.00
chip_sw_kmac_smoketest 229.710s 3588.002us 1 1 100.00
chip_sw_otbn_smoketest 1220.450s 9016.046us 1 1 100.00
chip_sw_pwrmgr_smoketest 294.280s 5501.344us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 376.020s 7134.212us 1 1 100.00
chip_sw_rv_plic_smoketest 174.050s 3027.951us 1 1 100.00
chip_sw_rv_timer_smoketest 177.710s 3090.623us 1 1 100.00
chip_sw_rstmgr_smoketest 138.490s 2866.627us 1 1 100.00
chip_sw_sram_ctrl_smoketest 175.380s 3042.998us 1 1 100.00
chip_sw_uart_smoketest 191.800s 3382.467us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 156.280s 3431.429us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 344.540s 5050.797us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8351.940s 64472.106us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3136.320s 16284.782us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 149.111s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 168.470s 3136.550us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 174.850s 2944.440us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7575.430s 54354.046us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7937.800s 58565.390us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 122.930s 2707.699us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 122.930s 2707.699us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4676.090s 32220.421us 1 1 100.00
chip_same_csr_outstanding 1768.810s 16699.932us 1 1 100.00
chip_csr_hw_reset 178.250s 4552.972us 1 1 100.00
chip_csr_rw 508.520s 6016.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4676.090s 32220.421us 1 1 100.00
chip_same_csr_outstanding 1768.810s 16699.932us 1 1 100.00
chip_csr_hw_reset 178.250s 4552.972us 1 1 100.00
chip_csr_rw 508.520s 6016.418us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 18.490s 256.790us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.320s 47.658us 1 1 100.00
xbar_smoke_large_delays 49.200s 8510.169us 1 1 100.00
xbar_smoke_slow_rsp 50.960s 5652.950us 1 1 100.00
xbar_random_zero_delays 7.560s 53.032us 1 1 100.00
xbar_random_large_delays 31.020s 4431.551us 1 1 100.00
xbar_random_slow_rsp 27.870s 3038.980us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 16.790s 186.276us 1 1 100.00
xbar_error_and_unmapped_addr 17.360s 582.273us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 41.310s 1602.169us 1 1 100.00
xbar_error_and_unmapped_addr 17.360s 582.273us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 24.900s 1191.578us 1 1 100.00
xbar_access_same_device_slow_rsp 298.040s 36485.603us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 32.120s 573.139us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 231.350s 8585.719us 1 1 100.00
xbar_stress_all_with_error 152.710s 3565.136us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 329.880s 10091.060us 1 1 100.00
xbar_stress_all_with_reset_error 63.980s 367.554us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3136.320s 16284.782us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3124.210s 38927.703us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3090.590s 15489.524us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 43.221s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 19.018s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 8.799s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 17.691s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 25.752s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 62.219s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 34.630s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 33.265s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 25.412s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 14.383s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 133.004s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 55.685s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 43.083s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 40.817s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 13.210s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.480s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 21.620s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.160s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.440s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.490s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 20.180s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 22.410s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 23.270s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.850s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.290s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.560s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.940s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.350s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.280s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 24.820s 10.320us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 68.603s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 65.991s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 108.896s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 74.378s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 112.834s 0.000us 0 1 0.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 6103.320s 33184.756us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3240.530s 16185.095us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3199.770s 15784.939us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3398.130s 17574.430us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3020.640s 35216.958us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3020.640s 35216.958us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 158.020s 3557.343us 1 1 100.00
chip_sw_aes_enc_jitter_en 189.850s 3286.858us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 161.680s 2641.041us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 161.730s 2764.053us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1637.780s 12881.751us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 183.880s 3151.602us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 454.800s 6391.841us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 569.140s 5369.208us 1 1 100.00
chip_plic_all_irqs_10 272.210s 3770.544us 1 1 100.00
chip_plic_all_irqs_20 368.690s 4516.285us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 205.460s 3365.428us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1123.930s 11665.889us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 332.670s 4696.091us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 130.120s 2437.159us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.162s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1092.780s 7725.896us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 977.150s 7029.556us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 850.000s 8176.811us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8059.380s 256762.026us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 223.710s 4132.080us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 294.280s 5501.344us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 223.710s 4132.080us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 487.470s 7690.852us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 487.470s 7690.852us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 310.660s 7699.018us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 448.130s 5549.718us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 598.160s 6112.026us 1 1 100.00
chip_sw_aes_idle 161.730s 2764.053us 1 1 100.00
chip_sw_hmac_enc_idle 205.890s 3398.997us 1 1 100.00
chip_sw_kmac_idle 135.320s 3050.223us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 220.690s 4076.464us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 227.040s 5516.530us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 277.790s 3652.270us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 310.710s 4375.772us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 841.570s 13300.701us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 409.470s 3899.587us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 386.980s 4847.997us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 379.830s 4547.343us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 413.940s 4910.390us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 393.830s 4305.621us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 372.640s 4689.804us 1 1 100.00
chip_sw_ast_clk_outputs 598.910s 8627.836us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 346.240s 7484.020us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 379.830s 4547.343us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 413.940s 4910.390us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 422.980s 4256.262us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 679.410s 6424.236us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3921.490s 18954.261us 1 1 100.00
chip_sw_aes_enc_jitter_en 189.850s 3286.858us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 671.330s 7298.236us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.240s 2833.382us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 870.730s 8542.815us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 157.620s 2530.032us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 393.810s 4648.711us 1 1 100.00
chip_sw_clkmgr_jitter 110.020s 2875.559us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 144.440s 2863.039us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 407.600s 5061.196us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 693.660s 7322.619us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3974.690s 25048.933us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 169.010s 2882.657us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 172.680s 2964.715us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 749.140s 8540.495us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 178.750s 3676.175us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 343.150s 5360.837us 1 1 100.00
chip_sw_flash_init_reduced_freq 1263.200s 22907.282us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 7165.830s 70925.386us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 598.910s 8627.836us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 415.420s 4693.669us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 266.070s 3488.061us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1092.780s 7725.896us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1955.330s 24012.337us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 145.000s 2543.888us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 581.860s 6907.402us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 163.560s 3602.648us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3829.150s 22454.841us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 147.170s 3044.067us 1 1 100.00
chip_sw_edn_entropy_reqs 610.410s 6805.148us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 147.170s 3044.067us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1955.330s 24012.337us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 176.440s 3099.741us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1040.670s 17958.982us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 562.070s 5841.720us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 679.410s 6424.236us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 386.220s 4517.486us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 422.980s 4256.262us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3516.710s 42956.187us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1040.670s 17958.982us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 260.280s 3972.730us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1044.750s 9984.232us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 131.510s 3057.783us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3516.710s 42956.187us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 131.510s 3057.783us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 131.510s 3057.783us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 131.510s 3057.783us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 131.510s 3057.783us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 298.460s 8818.207us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 581.960s 5889.302us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 368.190s 5312.265us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 368.190s 5312.265us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 189.820s 3535.568us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.240s 2833.382us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 205.890s 3398.997us 1 1 100.00
chip_sw_hmac_all_configurations 0 1 0.00
chip_sw_hmac_oneshot 1621.020s 12026.749us 0 1 0.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1859.950s 12018.552us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 428.390s 4755.369us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 475.250s 5920.300us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 486.500s 5094.023us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 294.380s 4495.543us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1044.750s 9984.232us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 870.730s 8542.815us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 783.230s 8377.898us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1637.780s 12881.751us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5122.310s 20018.719us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 178.160s 2684.091us 1 1 100.00
chip_sw_kmac_mode_kmac 196.820s 3109.712us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 157.620s 2530.032us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1044.750s 9984.232us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 158.720s 2885.465us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 945.310s 7245.604us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 135.320s 3050.223us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 454.800s 6391.841us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 881.910s 12791.078us 1 1 100.00
chip_tap_straps_rma 167.290s 3319.544us 1 1 100.00
chip_tap_straps_prod 1040.810s 15339.319us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 153.390s 2790.585us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1791.380s 13119.735us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 131.510s 3057.783us 0 1 0.00
chip_sw_flash_rma_unlocked 3516.710s 42956.187us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 186.130s 2767.161us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 569.720s 6846.542us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 615.340s 7462.683us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 505.040s 7825.576us 0 1 0.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_keymgr_key_derivation 1044.750s 9984.232us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 316.720s 10064.806us 1 1 100.00
chip_sw_sram_ctrl_execution_main 486.630s 9305.432us 1 1 100.00
chip_prim_tl_access 298.460s 8818.207us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 346.240s 7484.020us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 409.470s 3899.587us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 386.980s 4847.997us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 379.830s 4547.343us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 413.940s 4910.390us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 393.830s 4305.621us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 372.640s 4689.804us 1 1 100.00
chip_tap_straps_dev 881.910s 12791.078us 1 1 100.00
chip_tap_straps_rma 167.290s 3319.544us 1 1 100.00
chip_tap_straps_prod 1040.810s 15339.319us 1 1 100.00
chip_rv_dm_lc_disabled 138.750s 4195.992us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 145.080s 3429.799us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 97.160s 2954.546us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 73.270s 2685.952us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 165.210s 3706.698us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1662.080s 36908.247us 1 1 100.00
chip_rv_dm_lc_disabled 138.750s 4195.992us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 739.240s 11660.641us 0 1 0.00
chip_sw_lc_walkthrough_prod 607.620s 11025.438us 0 1 0.00
chip_sw_lc_walkthrough_prodend 687.870s 10837.033us 1 1 100.00
chip_sw_lc_walkthrough_rma 880.580s 26494.636us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1662.080s 36908.247us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 947.690s 26486.041us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 784.410s 26969.691us 0 1 0.00
rom_volatile_raw_unlock 141.029s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3874.070s 17131.594us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3921.490s 18954.261us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 598.160s 6112.026us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 598.160s 6112.026us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 598.160s 6112.026us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 324.050s 3755.771us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1040.670s 17958.982us 1 1 100.00
chip_sw_otbn_mem_scramble 324.050s 3755.771us 1 1 100.00
chip_sw_keymgr_key_derivation 1044.750s 9984.232us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 374.580s 4802.353us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 149.490s 3426.556us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1040.670s 17958.982us 1 1 100.00
chip_sw_otbn_mem_scramble 324.050s 3755.771us 1 1 100.00
chip_sw_keymgr_key_derivation 1044.750s 9984.232us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 374.580s 4802.353us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 149.490s 3426.556us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 344.500s 6100.562us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 153.390s 2790.585us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 186.130s 2767.161us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 569.720s 6846.542us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 615.340s 7462.683us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 505.040s 7825.576us 0 1 0.00
chip_sw_lc_ctrl_transition 335.360s 7611.391us 1 1 100.00
chip_prim_tl_access 298.460s 8818.207us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 298.460s 8818.207us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 923.000s 7137.023us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 79.250s 2790.741us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1154.960s 26518.947us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 259.930s 7267.644us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 257.920s 7395.003us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 478.590s 6376.365us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 717.600s 21030.609us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 445.310s 10568.700us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 487.470s 7690.852us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 496.480s 8785.468us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 386.020s 5770.455us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 79.250s 2790.741us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 320.910s 5782.271us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2374.030s 32633.459us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 311.090s 6566.061us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 190.390s 3456.778us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1393.790s 20146.832us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 673.460s 7823.939us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1092.720s 10895.346us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2063.870s 23691.038us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 181.310s 3329.657us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 316.720s 10064.806us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 316.720s 10064.806us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1092.720s 10895.346us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1393.790s 20146.832us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 386.020s 5770.455us 1 1 100.00
chip_sw_pwrmgr_smoketest 294.280s 5501.344us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 294.250s 4943.212us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 380.200s 5119.725us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 279.980s 4412.435us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1123.930s 11665.889us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 188.690s 3027.156us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 977.150s 7029.556us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 461.200s 5001.247us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 509.700s 4435.840us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 188.480s 3336.856us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 149.490s 3426.556us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 380.200s 5119.725us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 380.200s 5119.725us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 611.310s 10644.038us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 863.670s 14256.522us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 294.250s 4943.212us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 240.200s 3481.717us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 273.900s 6655.968us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 167.290s 3319.544us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 138.750s 4195.992us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 569.140s 5369.208us 1 1 100.00
chip_plic_all_irqs_10 272.210s 3770.544us 1 1 100.00
chip_plic_all_irqs_20 368.690s 4516.285us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 132.200s 2910.303us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 163.040s 2909.453us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3136.320s 16284.782us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 430.390s 5463.102us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 228.200s 3935.682us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 206.030s 3541.330us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 165.900s 3529.980us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 374.580s 4802.353us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 393.810s 4648.711us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 503.680s 8459.895us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 441.850s 8843.743us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 486.630s 9305.432us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
chip_sw_data_integrity_escalation 459.400s 5760.059us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 673.460s 7823.939us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1182.150s 24268.128us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 164.800s 2997.192us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 204.170s 3410.625us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 311.550s 4677.408us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1182.150s 24268.128us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1182.150s 24268.128us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2365.890s 20825.160us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2365.890s 20825.160us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 385.950s 6652.058us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3020.640s 35216.958us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 146.190s 2797.099us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 131.990s 2952.363us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 292.370s 3774.618us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 323.210s 4602.908us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1042.860s 8403.776us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5111.120s 31868.998us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1801.390s 11364.458us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 159.580s 2659.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 168.680s 2853.140us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 139.090s 2582.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9914.340s 71630.962us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1088.080s 6399.341us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 525.880s 6922.114us 0 1 0.00
rom_e2e_jtag_debug_dev 514.360s 5846.556us 0 1 0.00
rom_e2e_jtag_debug_rma 212.440s 4480.272us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 65.620s 2118.893us 0 1 0.00
rom_e2e_jtag_inject_dev 58.520s 1863.309us 0 1 0.00
rom_e2e_jtag_inject_rma 59.230s 2465.398us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 50.930s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 256.660s 3461.466us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 337.250s 3117.964us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 523.980s 4301.036us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 977.670s 7532.650us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 230.900s 2340.113us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 639.880s 5553.967us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 180.150s 3102.872us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 196.980s 3104.966us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 329.260s 6109.959us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 298.670s 5541.419us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1092.720s 10895.346us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 525.880s 6922.114us 0 1 0.00
rom_e2e_jtag_debug_dev 514.360s 5846.556us 0 1 0.00
rom_e2e_jtag_debug_rma 212.440s 4480.272us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 328.680s 6223.492us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 354.820s 4971.940us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5573.310s 38767.135us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5573.310s 38767.135us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 189.790s 3512.640us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 336.790s 4020.414us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2985.730s 18304.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 11 54.55
chip_sival_flash_info_access 190.860s 2790.150us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 23.250s 10.100us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.590s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 163.700s 3227.810us 1 1 100.00
chip_sw_otp_ctrl_descrambling 210.680s 3534.442us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 246.310s 3842.298us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.888s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 256.110s 3351.147us 1 1 100.00
ate_bootstrap_flash_erase 603.780s 10010.320us 0 1 0.00
ate_bootstrap_one_frame 6827.610s 44974.598us 1 1 100.00
ate_bootstrap_disjoint 10147.220s 84287.041us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 45553335244945094869775740732026672217930619902620791929542339673347576119460 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 44840227767168100831343408928478328135366221251421822947818479749060689419764 None
---- STDERR ----
Another command (pid=373791) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 68285734184551449990583744993262261242744058925526316955454058427715045433174 None
Another command (pid=664226) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=660371) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=660635) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 670130693369495091021987819564051578000607140320556262482095405661545591266 None
Another command (pid=618354) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=476435) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=647840) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 7476547995080487268897202077759581175975917048638151963684809244197518992212 None
Another command (pid=673139) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=680135) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=671571) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 22009324672202804315952730910360858872607928386169201117523970792607078242964 None
Another command (pid=666105) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=683099) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=699422) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 3754217831852406559070597562615454864219848601446217868364843748502577856689 None
Another command (pid=397136) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=402875) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=376772) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 38211887342171337780940519611438125133977133829546347777212332946488538039156 None
Another command (pid=574306) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=618058) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=593973) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 90139416054578543091914594241895452911585773617386682182970906287591026744502 None
Another command (pid=634032) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=574306) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=618058) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 1491247199592579158886077258813758100696615584515372994548931438384592135757 None
Another command (pid=418599) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=447753) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=634032) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 81625940289863379296273774208217638233723710100584777965216866694758945529931 None
Another command (pid=591556) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=632669) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=587470) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 49010099773995887615056658511619738072401191057986513681387641558896858525737 None
Another command (pid=431967) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=553087) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=452695) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 78006588200268301894371517068936626756678671703895399559064644152371666735763 None
Another command (pid=604033) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=574306) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=618058) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 97151718717527032531963318571645355452380649238693887400231810868336776681017 None
Another command (pid=418599) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=447753) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=634032) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 55950221739322589975571845021510732480794724120620136176794986629435200791613 None
Another command (pid=418599) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=447753) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=634032) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 96743235072606299767286163117738223100060380978152966777425574731008396617837 None
---- STDERR ----
Another command (pid=576413) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=559336) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 113041263768089757260624495975509563652421773240444930686219505762661648228727 None
Another command (pid=402875) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=376772) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=379606) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 79023428152764496243214947627629054691940651586715593691802001014347446379730 None
---- STDERR ----
Another command (pid=460636) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 4687614587597006126820152083524862371421968922061218769943120956245963063860 None
Another command (pid=634032) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=574306) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=618058) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 83244647505512255408318780151206110161216467215398241012419425787879041890236 None
Another command (pid=459643) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=559902) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=455727) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 32965894979900441650123580044136081964250050288333403444835172667682088595852 None
Another command (pid=634268) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=648167) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=634905) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 9383826182144104687240198305434791827629307063666918367136117943828807043960 None
Another command (pid=615792) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=593679) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=604912) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 98865857481081991755382593178890138243786273529054935651758627274031337498037 None
Another command (pid=589215) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=632669) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=587470) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 83376059201228560131155406493693771369597345848428428842609174107733435490440 None
Another command (pid=402875) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=376772) is running. Waiting for it to complete on the server (server_pid=275050)...
Another command (pid=379606) is running. Waiting for it to complete on the server (server_pid=275050)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 100846153140327176046831102671156180661009175823867669392379149788984141803430 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 13128265415379387238703501227696818674199095556635399540301813414733526523095 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 6172186832364469255897099629141201814926131602365864554030623649966452831877 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 34586488246873082250840995973308643877708597233992025730713436256411722531702 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 25228300845708392666792255518464607380734572570766940362752042443720948946982 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 108020494997442875576378343842305560885794392659773961594054011174535343112217 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 55813911356458775930085597927489309621250691538440911004835593280521171840310 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 33871695085264849656189426476420048394456974985729015662902567374454407977219 366
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 100972586234178195072637287466943648848867592479184391975924074635896229958234 367
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 12990920136544588174273914939172038667222751290651254789402217281272479152819 366
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 44816128119159420621710474548439269075463719086291557130305849173395658025319 327
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 99623160565775239689114102611876814643235680577018234231649213725864279716686 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 28796577205665845166588946531542894096366298651273160340290246284793099200686 326
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 3 test runs
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 31281818601559357914231575333117128367809857908855578078365006785703841204558 327
UVM_ERROR @ 10568.700000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10568.700000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 42179064445554862010500445418014888692363745328162029050208422747603555854314 325
UVM_ERROR @ 7395.003000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7395.003000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 19157556277749472740186123485540042074295072006929689383044478708961256594200 319
UVM_ERROR @ 7690.852000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7690.852000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_oneshot 2026463870585587019202071968320787000203083237409102602880903557827907220226 310
UVM_INFO @ 12026.749285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 115768738891450174115710886150505656894237695148333465833664524427414945428513 310
UVM_INFO @ 12018.551832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 111791423090127379159795080660620234665306384896683608341245511849870340181652 336
UVM_INFO @ 20018.718966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 43565622166397320707253582936621377274189189550503707389577968518740971982815 327
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 11547924020503693618757826224031920679111912579450654215573364535263796845834 328
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3445137715809373643246272058419040913451464945589431075368219920244498809582 325
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 83684204704702398358257933158550346568945102210525390985827435856759116129036 316
UVM_ERROR @ 3104.966312 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3104.966312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 20166393052425696770250944306275731480375340575996772758035161967034682250624 312
UVM_ERROR @ 2543.887898 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2543.887898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_dev 58081549276232770482474071722584289769756002103051983996423020964246705747961 369
UVM_INFO @ 11660.640616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 22958329230373597394311597435523147482326402219230263894551093643589147003104 369
UVM_INFO @ 11025.437512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 53850074199837864558427637352605065830447705738987181534481894723132481227608 218
TL item was: req: (cip_tl_seq_item@94862) { a_addr: 'h105a4 a_data: 'ha0bbd89f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1b667 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2707.698982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 31158980819373762750112359035105653765831283977849604917333398239617168806562 224
TL item was: req: (cip_tl_seq_item@31952) { a_addr: 'h10688 a_data: 'hf53de6e4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1bae8 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2268.479830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 18911204482064833162487151274312312966343243299324046225003497544467507984378 362
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 35148986217973862394959315958029204721617388788944237607451973392334097061139 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 45382553621378316114972404176881947327514259372601122460788572758343023349287 368
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 91157228079169534031550269047748418170108087836112457270402404581506740218051 326
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 50262309061744622371624694326406532526966608225553904686746787713984256109704 301
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 36901131239228522963527547856671620300312045811058470655293624038838493647206 451
UVM_INFO @ 2875.444000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 105455940729752161566043434732378471687722087592432042084164764220677475447292 327
UVM_INFO @ 3935.682380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 96005359961649539700177507103458289224600201411459544070869652607824314483939 309
UVM_INFO @ 3057.782817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 94558804889865659104108230862812884754815518943466965281024275423679583927731 342
UVM_INFO @ 7825.575512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 66486635959063307634219125660317770430990592805980963283748726696098367201393 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 47521261710965995674850661844470980885903440665137620785392654264877038396319 308
UVM_INFO @ 26486.041031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 114328242082870313823834661322677325898622289467396283544269902711951946215025 309
UVM_INFO @ 26969.691023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_rma 94280198347017770400626522574279635141610383594157934331140159381263010270124 308
UVM_INFO @ 26494.635974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 115050754324691424242189050959089416982117605245205806801229401746718546882147 303
UVM_ERROR @ 2790.741080 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2790.741080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 1 test run
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 87358503097415258473238663547599467926648496774347893026899069240804082539392 341
UVM_ERROR @ 8785.467816 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 8785.467816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 73504689111220027199779810546752996344252693769531479496366349862791963430818 313
UVM_ERROR @ 3456.777711 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3456.777711 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 68578845524723611442926749486381076535341006378278180618900185561242323298955 332
UVM_INFO @ 35216.957690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 54378850788596949143472660997063013098283729518957182185672477968111819162094 307
UVM_INFO @ 3151.601998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 22664796187463252912916243016182495153095731188678014090450631961982940600885 308
UVM_INFO @ 2437.158957 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 36545400783570475689312781258801344451096392306670020131184198873713502070293 None
Offending '(reset_cause == HwReq)' 1 test run
chip_sw_sensor_ctrl_alert 54461847490875026650954984260080236768143912115642951290255019514220166415119 331
UVM_ERROR @ 5264.799672 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 5264.799672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 56063835618230632288899456458610641335396671985585983294120856445604251779464 343
UVM_INFO @ 3461.466489 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() 1 test run
chip_sw_pwrmgr_lowpower_cancel 110170899485420504944713923661295389875434752135631426025947181268856983369738 317
UVM_INFO @ 3842.298480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 58701314231920645964981876416245223228565208192941904091088365421645880181420 226
UVM_INFO @ 4195.992228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 10582597637555264908907207921538237142453825856631022097796639870444938386364 314
UVM_INFO @ 3136.550000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 78179733390986850091013112430174646844317700508374272436375663642640081288111 318
UVM_INFO @ 2944.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 2681962701832804317005218211759342221097083453268231879315394748337779691757 327
UVM_INFO @ 9430.522291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 37547328142632837250415691445292778954269099725705827342381344889994719367672 272
UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 78898137491642182527767200071108111156748419459606947455445306418833747812757 325
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 102323618728184631671213885828236103645027735315314241413044365875278423489262 328
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 68009809503960643603716293323179732532415786988130023927486493053440330944888 319
UVM_INFO @ 16185.094944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 69142681276097382601430789696043421526481621756306838685304504449523799824548 319
UVM_INFO @ 15784.938804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 45890916676015617603624344555941436153289527176786370339157501746178021561539 327
UVM_ERROR @ 5050.797277 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5050.797277 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---