Simulation Results: clkmgr

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.20 %
  • code
  • 97.61 %
  • assert
  • 94.07 %
  • func
  • 84.91 %
  • line
  • 98.93 %
  • branch
  • 98.27 %
  • cond
  • 91.66 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.890s 66.258us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.780s 15.732us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.810s 1193.701us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.390s 53.740us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.270s 165.451us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
clkmgr_csr_aliasing 1.390s 53.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.820s 15.216us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.840s 17.201us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.850s 71.007us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.620s 24.124us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.890s 66.258us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 8.470s 2391.023us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.990s 500.907us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 8.470s 2391.023us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 18.440s 8104.731us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.740s 17.488us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.860s 155.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.860s 155.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 15.732us 1 1 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
clkmgr_csr_aliasing 1.390s 53.740us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 41.856us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.780s 15.732us 1 1 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
clkmgr_csr_aliasing 1.390s 53.740us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 41.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 31.420s 10122.183us 0 1 0.00
clkmgr_tl_intg_err 1.410s 58.594us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 459.040s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 459.040s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 459.040s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 459.040s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.460s 257.670us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.410s 58.594us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 8.470s 2391.023us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.990s 500.907us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 459.040s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.870s 81.320us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.820s 23.633us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.080s 25.775us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.710s 16.917us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.640s 23.592us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 31.420s 10122.183us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 32.271us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 31.420s 10122.183us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.700s 543.222us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 29.100s 4155.847us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 53813302634581210566263852884098448116831806014903852279521731284372563642520 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 32972849049606146884596097558252484203885470994233442450111303059544801823339 151
UVM_INFO @ 10122183292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---