Simulation Results: csrng

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.88 %
  • code
  • 92.26 %
  • assert
  • 94.54 %
  • func
  • 79.84 %
  • block
  • 96.85 %
  • line
  • 97.69 %
  • branch
  • 92.26 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 34.020us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 23.387us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 21.097us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 21.000s 558.473us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 44.833us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 18.515us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 21.097us 1 1 100.00
csrng_csr_aliasing 3.000s 44.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
alerts 1 1 100.00
csrng_alert 14.000s 1169.117us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 10.000s 501.612us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 10.000s 501.612us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 488.000s 33035.063us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 14.929us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 70.005us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 82.658us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 82.658us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 23.387us 1 1 100.00
csrng_csr_rw 2.000s 21.097us 1 1 100.00
csrng_csr_aliasing 3.000s 44.833us 1 1 100.00
csrng_same_csr_outstanding 2.000s 46.497us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 23.387us 1 1 100.00
csrng_csr_rw 2.000s 21.097us 1 1 100.00
csrng_csr_aliasing 3.000s 44.833us 1 1 100.00
csrng_same_csr_outstanding 2.000s 46.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
csrng_tl_intg_err 5.000s 347.170us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 4.934us 0 1 0.00
csrng_csr_rw 2.000s 21.097us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 14.000s 1169.117us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 488.000s 33035.063us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 14.000s 1169.117us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 488.000s 33035.063us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 14.000s 1169.117us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 347.170us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
csrng_sec_cm 3.000s 79.189us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 92.261us 1 1 100.00
csrng_err 2.000s 21.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 44608022672707245481172732041697908548114838786549046761947870370349833949545 99
UVM_INFO @ 4933923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 96162890073912304418839109107281074409177491849857785111087650907062992108628 None