Simulation Results: edn/edn0

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.95 %
  • code
  • 80.98 %
  • assert
  • 96.31 %
  • func
  • 80.56 %
  • line
  • 97.55 %
  • branch
  • 91.21 %
  • cond
  • 86.65 %
  • toggle
  • 78.96 %
  • FSM
  • 50.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 28.500us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 84.005us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 43.839us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.140s 318.321us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 37.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.190s 18.899us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 43.839us 1 1 100.00
edn_csr_aliasing 1.160s 37.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.180s 37.170us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.180s 37.170us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.180s 37.170us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 27.937us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 64.980us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 27.932us 1 1 100.00
disable 2 2 100.00
edn_disable 0.890s 58.560us 1 1 100.00
edn_disable_auto_req_mode 0.930s 50.020us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.840s 299.683us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 87.780us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 24.830us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.900s 73.586us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.900s 73.586us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 84.005us 1 1 100.00
edn_csr_rw 0.830s 43.839us 1 1 100.00
edn_csr_aliasing 1.160s 37.625us 1 1 100.00
edn_same_csr_outstanding 0.950s 45.136us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 84.005us 1 1 100.00
edn_csr_rw 0.830s 43.839us 1 1 100.00
edn_csr_aliasing 1.160s 37.625us 1 1 100.00
edn_same_csr_outstanding 0.950s 45.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.800s 1027.304us 1 1 100.00
edn_tl_intg_err 1.380s 637.742us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.010s 20.324us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 64.980us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.800s 1027.304us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.800s 1027.304us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.800s 1027.304us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.800s 1027.304us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 64.980us 1 1 100.00
edn_sec_cm 10.800s 1027.304us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 64.980us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.380s 637.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 58.590s 7222.479us 1 1 100.00