Simulation Results: edn/edn1

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.57 %
  • code
  • 84.28 %
  • assert
  • 98.18 %
  • func
  • 80.25 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 89.31 %
  • toggle
  • 94.42 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.910s 48.962us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 16.871us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 44.952us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.640s 47.555us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 77.452us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.880s 64.429us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 44.952us 1 1 100.00
edn_csr_aliasing 1.150s 77.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.970s 68.360us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.970s 68.360us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.970s 68.360us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 40.468us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.320s 93.486us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 38.930us 1 1 100.00
disable 2 2 100.00
edn_disable 0.830s 20.007us 1 1 100.00
edn_disable_auto_req_mode 0.940s 84.624us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.370s 2787.278us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.940s 27.093us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 55.319us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.950s 276.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.950s 276.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 16.871us 1 1 100.00
edn_csr_rw 0.850s 44.952us 1 1 100.00
edn_csr_aliasing 1.150s 77.452us 1 1 100.00
edn_same_csr_outstanding 0.940s 362.034us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 16.871us 1 1 100.00
edn_csr_rw 0.850s 44.952us 1 1 100.00
edn_csr_aliasing 1.150s 77.452us 1 1 100.00
edn_same_csr_outstanding 0.940s 362.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.180s 145.924us 1 1 100.00
edn_tl_intg_err 1.310s 80.390us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.830s 246.331us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.320s 93.486us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.180s 145.924us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.180s 145.924us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.180s 145.924us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.180s 145.924us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.320s 93.486us 1 1 100.00
edn_sec_cm 2.180s 145.924us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.320s 93.486us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.310s 80.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.440s 1322.221us 1 1 100.00