Simulation Results: flash_ctrl

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 94.01 %
  • assert
  • 97.02 %
  • func
  • 95.79 %
  • line
  • 95.98 %
  • branch
  • 97.16 %
  • cond
  • 93.76 %
  • toggle
  • 97.44 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 34.920s 36.451us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.850s 62.005us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 13.760s 20.233us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 60.880s 7991.165us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 41.350s 2022.387us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.360s 48.131us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
flash_ctrl_csr_aliasing 41.350s 2022.387us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 8.680s 92.657us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.050s 129.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.250s 30.867us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 20.750s 119.170us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1297.420s 170972.682us 1 1 100.00
flash_ctrl_hw_rma_reset 515.950s 40123.870us 1 1 100.00
flash_ctrl_lcmgr_intg 6.680s 23.934us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1410.750s 257301.702us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 154.020s 5611.891us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.190s 21.712us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1781.090s 106936.300us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 49.550s 3099.356us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.300s 148.167us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.270s 256.055us 1 1 100.00
flash_ctrl_re_evict 15.010s 195.690us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 74.870s 224.113us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 74.870s 224.113us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 194.430s 24506.217us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 20.110s 7954.191us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 177.770s 209.443us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 386.360s 3073.510us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 281.320s 1593.027us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 776.530s 852.144us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.260s 23.776us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 126.390s 12180.202us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.980s 19.301us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.650s 28.213us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 444.150s 955.747us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 101.360s 44346.925us 1 1 100.00
flash_ctrl_otp_reset 61.220s 125.197us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1297.420s 170972.682us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 145.870s 2059.847us 1 1 100.00
flash_ctrl_intr_wr 70.860s 10034.450us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 99.230s 5522.449us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 124.260s 32913.158us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 47.730s 2875.284us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 38.190s 2548.810us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 12.200s 113.030us 1 1 100.00
flash_ctrl_ro_derr 100.410s 2642.966us 1 1 100.00
flash_ctrl_rw_derr 123.700s 6618.098us 1 1 100.00
flash_ctrl_derr_detect 92.440s 2674.390us 1 1 100.00
flash_ctrl_integrity 451.460s 8819.427us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 15.650s 106.844us 1 1 100.00
flash_ctrl_ro_serr 99.840s 3476.988us 1 1 100.00
flash_ctrl_rw_serr 132.580s 1466.016us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 31.420s 545.648us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 36.860s 1239.395us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 89.890s 6048.869us 1 1 100.00
flash_ctrl_write_word_sweep 7.030s 465.544us 1 1 100.00
flash_ctrl_read_word_sweep 6.980s 56.603us 1 1 100.00
flash_ctrl_ro 90.870s 2806.281us 1 1 100.00
flash_ctrl_rw 351.300s 4778.700us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.670s 391.471us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 590.390s 123080.643us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 32.470s 10049.772us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 7.650s 64.248us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.340s 46.397us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.950s 66.677us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.950s 66.677us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.760s 20.233us 1 1 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
flash_ctrl_csr_aliasing 41.350s 2022.387us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.850s 65.903us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.760s 20.233us 1 1 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
flash_ctrl_csr_aliasing 41.350s 2022.387us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.850s 65.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 19.580s 54.525us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
flash_ctrl_tl_intg_err 202.920s 2203.198us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 202.920s 2203.198us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 202.920s 2203.198us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.920s 78.552us 1 1 100.00
flash_ctrl_wr_intg 6.810s 48.539us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 34.920s 36.451us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 61.220s 125.197us 1 1 100.00
flash_ctrl_disable 10.980s 19.301us 1 1 100.00
flash_ctrl_sec_info_access 42.120s 7374.653us 1 1 100.00
flash_ctrl_connect 7.650s 28.213us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.870s 41.020us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.430s 163.667us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.150s 33.155us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.980s 19.301us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.920s 78.552us 1 1 100.00
flash_ctrl_access_after_disable 6.010s 22.103us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 17.800s 47.005us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.980s 19.301us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 20.110s 7954.191us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 351.300s 4778.700us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 132.580s 1466.016us 1 1 100.00
flash_ctrl_rw_derr 123.700s 6618.098us 1 1 100.00
flash_ctrl_integrity 451.460s 8819.427us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1297.420s 170972.682us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 13.040s 714.113us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.330s 80.736us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.070s 131.209us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.590s 5417.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.820s 54.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 212.350s 527.003us 1 1 100.00