Simulation Results: hmac

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.86 %
  • code
  • 97.80 %
  • assert
  • 97.38 %
  • func
  • 44.39 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.900s 6160.721us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 19.432us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.060s 32.536us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.100s 1894.028us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.630s 624.770us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 72.900s 10397.334us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.060s 32.536us 1 1 100.00
hmac_csr_aliasing 5.630s 624.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 3.090s 160.168us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 57.270s 13015.637us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.110s 461.568us 1 1 100.00
hmac_test_sha384_vectors 358.180s 32556.737us 1 1 100.00
hmac_test_sha512_vectors 23.250s 1367.599us 1 1 100.00
hmac_test_hmac256_vectors 9.560s 1476.268us 1 1 100.00
hmac_test_hmac384_vectors 10.740s 1964.165us 1 1 100.00
hmac_test_hmac512_vectors 10.220s 1309.310us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.080s 814.052us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 854.300s 91277.970us 1 1 100.00
error 1 1 100.00
hmac_error 35.360s 16711.543us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 61.460s 8344.214us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.900s 6160.721us 1 1 100.00
hmac_long_msg 3.090s 160.168us 1 1 100.00
hmac_back_pressure 57.270s 13015.637us 1 1 100.00
hmac_datapath_stress 854.300s 91277.970us 1 1 100.00
hmac_burst_wr 6.080s 814.052us 1 1 100.00
hmac_stress_all 303.210s 48133.985us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.900s 6160.721us 1 1 100.00
hmac_long_msg 3.090s 160.168us 1 1 100.00
hmac_back_pressure 57.270s 13015.637us 1 1 100.00
hmac_datapath_stress 854.300s 91277.970us 1 1 100.00
hmac_wipe_secret 61.460s 8344.214us 1 1 100.00
hmac_test_sha256_vectors 8.110s 461.568us 1 1 100.00
hmac_test_sha384_vectors 358.180s 32556.737us 1 1 100.00
hmac_test_sha512_vectors 23.250s 1367.599us 1 1 100.00
hmac_test_hmac256_vectors 9.560s 1476.268us 1 1 100.00
hmac_test_hmac384_vectors 10.740s 1964.165us 1 1 100.00
hmac_test_hmac512_vectors 10.220s 1309.310us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.900s 6160.721us 1 1 100.00
hmac_long_msg 3.090s 160.168us 1 1 100.00
hmac_back_pressure 57.270s 13015.637us 1 1 100.00
hmac_datapath_stress 854.300s 91277.970us 1 1 100.00
hmac_burst_wr 6.080s 814.052us 1 1 100.00
hmac_error 35.360s 16711.543us 1 1 100.00
hmac_wipe_secret 61.460s 8344.214us 1 1 100.00
hmac_test_sha256_vectors 8.110s 461.568us 1 1 100.00
hmac_test_sha384_vectors 358.180s 32556.737us 1 1 100.00
hmac_test_sha512_vectors 23.250s 1367.599us 1 1 100.00
hmac_test_hmac256_vectors 9.560s 1476.268us 1 1 100.00
hmac_test_hmac384_vectors 10.740s 1964.165us 1 1 100.00
hmac_test_hmac512_vectors 10.220s 1309.310us 1 1 100.00
hmac_stress_all 303.210s 48133.985us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 303.210s 48133.985us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 41.681us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.730s 81.553us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.360s 76.679us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.360s 76.679us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 19.432us 1 1 100.00
hmac_csr_rw 1.060s 32.536us 1 1 100.00
hmac_csr_aliasing 5.630s 624.770us 1 1 100.00
hmac_same_csr_outstanding 1.480s 34.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 19.432us 1 1 100.00
hmac_csr_rw 1.060s 32.536us 1 1 100.00
hmac_csr_aliasing 5.630s 624.770us 1 1 100.00
hmac_same_csr_outstanding 1.480s 34.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.830s 159.585us 1 1 100.00
hmac_tl_intg_err 2.280s 451.260us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.280s 451.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.900s 6160.721us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.120s 430.084us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 52.940s 14115.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.650s 89.756us 1 1 100.00