Simulation Results

Simulation Results: i2c

16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.59 %

code
81.61 %

assert
97.25 %

func
77.91 %

line
96.45 %

branch
92.33 %

cond
85.16 %

toggle
89.45 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	17.000s	3606.440us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	20.480s	2152.303us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.030s	24.951us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.780s	16.173us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.490s	3500.881us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.770s	414.871us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.060s	38.318us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.780s	16.173us	1	1	100.00
	i2c_csr_aliasing	1.770s	414.871us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.980s	108.948us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	428.660s	9136.110us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	34.860s	5492.024us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.900s	74.550us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	75.080s	5841.062us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	70.130s	23280.935us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.930s	319.820us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.820s	1598.575us	1	1	100.00
	i2c_host_fifo_reset_rx	3.350s	236.403us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	59.790s	2235.166us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	18.820s	625.979us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.870s	323.639us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.010s	3723.453us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	22.210s	5939.498us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.270s	3171.956us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.290s	901.721us	1	1	100.00
	i2c_target_intr_smoke	4.910s	5885.235us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.200s	879.387us	1	1	100.00
	i2c_target_fifo_reset_tx	0.930s	705.157us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	78.170s	28443.632us	1	1	100.00
	i2c_target_stress_rd	11.290s	901.721us	1	1	100.00
	i2c_target_intr_stress_wr	76.010s	15678.519us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.600s	1392.663us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	11.810s	1037.515us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.250s	8044.688us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	9.260s	10048.036us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.860s	1532.778us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.100s	2514.183us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	34.860s	5492.024us	1	1	100.00
	i2c_host_perf_precise	86.330s	24831.597us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	18.820s	625.979us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.140s	166.704us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.350s	1369.729us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.270s	2154.538us	1	1	100.00
	i2c_target_nack_txstretch	1.300s	2711.514us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.150s	537.838us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.440s	409.311us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.820s	17.328us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.950s	25.339us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.230s	158.151us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.230s	158.151us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.030s	24.951us	1	1	100.00
	i2c_csr_rw	0.780s	16.173us	1	1	100.00
	i2c_csr_aliasing	1.770s	414.871us	1	1	100.00
	i2c_same_csr_outstanding	1.190s	87.206us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.030s	24.951us	1	1	100.00
	i2c_csr_rw	0.780s	16.173us	1	1	100.00
	i2c_csr_aliasing	1.770s	414.871us	1	1	100.00
	i2c_same_csr_outstanding	1.190s	87.206us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.490s	349.817us	1	1	100.00
	i2c_sec_cm	0.770s	44.431us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.490s	349.817us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	20.180s	9154.487us	1
target_error_intr				1
	i2c_target_unexp_stop	0.930s	49.555us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	5.590s	716.442us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	95849901362159567961460204250868628677939532342867912948147647099946761193192	88	UVM_INFO @ 108947884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	3449479330900150061573192008891246977785809660365586835298772647189474957708	149	UVM_INFO @ 9136109612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	81307823741323236889848673398589664359287871327086607688625515499439172987480	98	UVM_INFO @ 716441890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	9212426504055408610915922153126014624574848620946681572521427328799522974079	84	UVM_INFO @ 3723452975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	11777094405276974103384816580230520986960018918017490184555713378335423437545	78	UVM_INFO @ 49555047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	94507275441914188008856933713015400955123421700429513285045914829999177018947	79	UVM_INFO @ 10048035842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	8162953885537128299820076445338007130243071104804557630704261759595219644735	92	UVM_INFO @ 9154486660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---