Simulation Results: keymgr

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.76 %
  • code
  • 93.41 %
  • assert
  • 97.49 %
  • func
  • 57.39 %
  • line
  • 98.72 %
  • branch
  • 97.44 %
  • cond
  • 93.80 %
  • toggle
  • 91.02 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.270s 115.760us 1 1 100.00
random 1 1 100.00
keymgr_random 3.300s 337.730us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.010s 19.185us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 8.050s 3175.195us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.090s 72.083us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.270s 185.614us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
keymgr_csr_aliasing 3.090s 72.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.520s 197.105us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.930s 159.421us 1 1 100.00
keymgr_sideload_kmac 3.180s 137.076us 1 1 100.00
keymgr_sideload_aes 2.440s 458.636us 1 1 100.00
keymgr_sideload_otbn 1.510s 95.196us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.550s 413.619us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.850s 597.155us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 4.000s 291.430us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 17.380s 2691.504us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.780s 116.500us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.280s 395.178us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 5.590s 324.762us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.760s 27.725us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.790s 296.810us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.730s 169.135us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.730s 169.135us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.010s 19.185us 1 1 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
keymgr_csr_aliasing 3.090s 72.083us 1 1 100.00
keymgr_same_csr_outstanding 2.150s 503.315us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.010s 19.185us 1 1 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
keymgr_csr_aliasing 3.090s 72.083us 1 1 100.00
keymgr_same_csr_outstanding 2.150s 503.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
keymgr_tl_intg_err 5.310s 1149.991us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.470s 160.122us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.470s 160.122us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.470s 160.122us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.470s 160.122us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.290s 300.497us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.310s 1149.991us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.470s 160.122us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.520s 197.105us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.300s 337.730us 1 1 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.300s 337.730us 1 1 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.300s 337.730us 1 1 100.00
keymgr_csr_rw 1.050s 12.580us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.850s 597.155us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.780s 116.500us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.780s 116.500us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.300s 337.730us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 8.090s 1830.559us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.060s 779.153us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.850s 597.155us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.060s 779.153us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.060s 779.153us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.060s 779.153us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 18.930s 1091.142us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.060s 779.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 2.980s 592.128us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 1771708777043188837050425166213897077192054680697905718172586940718242387758 401
UVM_INFO @ 592128163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---