| V1 |
|
100.00% |
| V2 |
|
68.97% |
| V2S |
|
87.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| kmac_smoke | 1.980s | 69.412us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| kmac_csr_hw_reset | 1.150s | 59.851us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| kmac_csr_rw | 0.890s | 26.316us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| kmac_csr_bit_bash | 6.360s | 228.993us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| kmac_csr_aliasing | 4.050s | 227.379us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 1.640s | 25.225us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| kmac_csr_rw | 0.890s | 26.316us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 4.050s | 227.379us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| kmac_mem_walk | 0.900s | 16.199us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| kmac_mem_partial_access | 1.380s | 39.308us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 1 | 1 | 100.00 | |||
| kmac_long_msg_and_output | 1591.030s | 353960.800us | 1 | 1 | 100.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 478.500s | 16349.596us | 1 | 1 | 100.00 | |
| test_vectors | 8 | 8 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 35.550s | 11664.886us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_256 | 1560.800s | 137165.449us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 1103.590s | 20483.393us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_512 | 16.070s | 1552.894us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 1865.880s | 30912.098us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 2363.710s | 1800335.722us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 2.360s | 437.825us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 2.000s | 58.160us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 211.780s | 50651.471us | 1 | 1 | 100.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 3.700s | 637.908us | 0 | 1 | 0.00 | |
| app_with_partial_data | 0 | 1 | 0.00 | |||
| kmac_app_with_partial_data | 2.980s | 144.215us | 0 | 1 | 0.00 | |
| entropy_refresh | 0 | 1 | 0.00 | |||
| kmac_entropy_refresh | 1.020s | 9.921us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| kmac_error | 2.390s | 85.089us | 0 | 1 | 0.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 1.060s | 31.495us | 0 | 1 | 0.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 1.190s | 17.151us | 0 | 1 | 0.00 | |
| edn_timeout_error | 1 | 1 | 100.00 | |||
| kmac_edn_timeout_error | 0.850s | 23.143us | 1 | 1 | 100.00 | |
| entropy_mode_error | 0 | 1 | 0.00 | |||
| kmac_entropy_mode_error | 25.070s | 5738.691us | 0 | 1 | 0.00 | |
| entropy_ready_error | 0 | 1 | 0.00 | |||
| kmac_entropy_ready_error | 1.350s | 61.276us | 0 | 1 | 0.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.450s | 46.610us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| kmac_stress_all | 30.750s | 4760.509us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| kmac_intr_test | 0.850s | 27.944us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.980s | 18.069us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 1.180s | 82.046us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 1.180s | 82.046us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 1.150s | 59.851us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.890s | 26.316us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 4.050s | 227.379us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.140s | 419.715us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 1.150s | 59.851us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.890s | 26.316us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 4.050s | 227.379us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.140s | 419.715us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.840s | 309.520us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.840s | 309.520us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.840s | 309.520us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.840s | 309.520us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 3.890s | 802.427us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| kmac_sec_cm | 62.050s | 5604.426us | 1 | 1 | 100.00 | |
| kmac_tl_intg_err | 2.760s | 396.635us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| kmac_tl_intg_err | 2.760s | 396.635us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.450s | 46.610us | 1 | 1 | 100.00 | |
| sec_cm_sw_key_key_masking | 1 | 1 | 100.00 | |||
| kmac_smoke | 1.980s | 69.412us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 211.780s | 50651.471us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.840s | 309.520us | 1 | 1 | 100.00 | |
| sec_cm_fsm_sparse | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 62.050s | 5604.426us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 62.050s | 5604.426us | 1 | 1 | 100.00 | |
| sec_cm_packer_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 62.050s | 5604.426us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 1 | 1 | 100.00 | |||
| kmac_smoke | 1.980s | 69.412us | 1 | 1 | 100.00 | |
| sec_cm_fsm_global_esc | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.450s | 46.610us | 1 | 1 | 100.00 | |
| sec_cm_fsm_local_esc | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 62.050s | 5604.426us | 1 | 1 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 0 | 1 | 0.00 | |||
| kmac_mubi | 5.790s | 694.675us | 0 | 1 | 0.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 1 | 1 | 100.00 | |||
| kmac_smoke | 1.980s | 69.412us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 2.330s | 58.430us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] | 7 test runs | |||
| kmac_sideload_invalid | 23359726468684597795350208696687836966143298141004227312599915894072319782963 | 76 |
UVM_INFO @ 17150805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app | 108095773203619554313482943100910661559845624618544336815594706708148987307335 | 78 |
UVM_INFO @ 637908354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app_with_partial_data | 12810375708468403785889335980037617376467119186042208628842435330324244005476 | 78 |
UVM_INFO @ 144214687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_refresh | 81973229821387035390705130686039978269427683329830081940618588697932587246796 | 77 |
UVM_INFO @ 9920784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_error | 53937838367905429196593849677729101109492208387114423905841034719325321282765 | 78 |
UVM_INFO @ 85089284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_ready_error | 38368816955865232276426130508544812757617988259887905286049118138768406170846 | 77 |
UVM_INFO @ 61275513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all_with_rand_reset | 89076240596306798853591333024437942551693864590552236733394158647914392291484 | 117 |
UVM_INFO @ 58430081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) | 2 test runs | |||
| kmac_mubi | 25383726796412968519504625731898411139074253550805309255408371254976215905311 | 79 |
UVM_INFO @ 694675247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all | 35946515640686825615155386769090111973015650830135297238119205315959051537952 | 111 |
UVM_INFO @ 4760508694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' | 2 test runs | |||
| kmac_key_error | 59600266745074561272663074749204657994743010041891974893666969189924776176663 | 78 |
UVM_ERROR @ 31494577 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 31494577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_mode_error | 10602070554020318137116140103820332262751725172198419268128530562012274485679 | 88 |
UVM_ERROR @ 5738690859 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 5738690859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|