Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.67 %
  • code
  • 84.27 %
  • assert
  • 94.69 %
  • func
  • 93.06 %
  • line
  • 97.20 %
  • branch
  • 93.85 %
  • cond
  • 79.65 %
  • toggle
  • 87.09 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.450s 169.039us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.940s 57.054us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 89.521us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.870s 150.537us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 72.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.270s 102.536us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 89.521us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 72.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.070s 72.202us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.940s 438.570us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 49.139us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.840s 54.853us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.050s 393.173us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_prog_failure 1.840s 54.853us 1 1 100.00
lc_ctrl_errors 8.050s 393.173us 1 1 100.00
lc_ctrl_security_escalation 4.710s 1343.622us 1 1 100.00
lc_ctrl_jtag_state_failure 34.930s 2789.012us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.860s 66.301us 1 1 100.00
lc_ctrl_jtag_errors 60.700s 3523.166us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.620s 910.041us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.740s 974.879us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.860s 66.301us 1 1 100.00
lc_ctrl_jtag_errors 60.700s 3523.166us 1 1 100.00
lc_ctrl_jtag_access 2.910s 5621.789us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.350s 2033.840us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.350s 368.370us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.960s 56.908us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.270s 1590.115us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.280s 823.743us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.210s 32.521us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.050s 157.502us 1 1 100.00
lc_ctrl_jtag_alert_test 0.950s 102.094us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.900s 1256.891us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.820s 44.160us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 294.130s 57039.739us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.380s 100.215us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.210s 24.437us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.210s 24.437us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 57.054us 1 1 100.00
lc_ctrl_csr_rw 1.030s 89.521us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 72.479us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.320s 14.821us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 57.054us 1 1 100.00
lc_ctrl_csr_rw 1.030s 89.521us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 72.479us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.320s 14.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
lc_ctrl_tl_intg_err 1.980s 112.106us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.980s 112.106us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.940s 438.570us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.610s 161.817us 1 1 100.00
lc_ctrl_sec_cm 5.620s 276.213us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.710s 1343.622us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.070s 72.202us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.740s 974.879us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.760s 1762.719us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.760s 1762.719us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.330s 1685.413us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.290s 927.182us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.290s 927.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.360s 3500.117us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 86122872917387413154358499710463375590770451294549866612462758490629084303914 1377
UVM_INFO @ 3500117415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---