Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.95 %
  • code
  • 82.80 %
  • assert
  • 94.69 %
  • func
  • 92.35 %
  • line
  • 97.17 %
  • branch
  • 93.37 %
  • cond
  • 79.41 %
  • toggle
  • 80.49 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.690s 131.497us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.880s 98.282us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 28.806us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.380s 100.435us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 66.405us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.470s 94.114us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 28.806us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 66.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.980s 101.453us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.860s 627.398us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.070s 42.075us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.750s 228.998us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.230s 401.184us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_prog_failure 1.750s 228.998us 1 1 100.00
lc_ctrl_errors 8.230s 401.184us 1 1 100.00
lc_ctrl_security_escalation 6.650s 6077.049us 1 1 100.00
lc_ctrl_jtag_state_failure 64.810s 3455.237us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.100s 115.351us 1 1 100.00
lc_ctrl_jtag_errors 6.320s 597.662us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 1.960s 126.113us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.810s 1376.606us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.100s 115.351us 1 1 100.00
lc_ctrl_jtag_errors 6.320s 597.662us 0 1 0.00
lc_ctrl_jtag_access 2.100s 176.464us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.470s 918.804us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.630s 194.002us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.340s 206.967us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.050s 1476.079us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.260s 2770.373us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.400s 43.716us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.880s 278.287us 1 1 100.00
lc_ctrl_jtag_alert_test 1.200s 73.976us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.510s 100.124us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 24.771us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 98.580s 9900.387us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 46.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.700s 140.749us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.700s 140.749us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 98.282us 1 1 100.00
lc_ctrl_csr_rw 0.830s 28.806us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 66.405us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.370s 18.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 98.282us 1 1 100.00
lc_ctrl_csr_rw 0.830s 28.806us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 66.405us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.370s 18.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
lc_ctrl_tl_intg_err 2.370s 85.358us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.370s 85.358us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.860s 627.398us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.740s 595.334us 1 1 100.00
lc_ctrl_sec_cm 6.130s 1305.988us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.650s 6077.049us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.980s 101.453us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.810s 1376.606us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.660s 354.598us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.660s 354.598us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.630s 5401.217us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.210s 888.975us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.210s 888.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 52.280s 2603.375us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 112811604650903560555057365145392031762372618763629883450047807123692083262375 883
UVM_INFO @ 597662224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 79591884217471775797193451161268662744700171837471728626249464427268269963211 4029
UVM_INFO @ 2603374942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---