Simulation Results: otbn

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.09 %
  • code
  • 94.25 %
  • assert
  • 90.14 %
  • func
  • 97.88 %
  • block
  • 99.34 %
  • line
  • 99.51 %
  • branch
  • 91.48 %
  • toggle
  • 88.45 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 55.004us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 29.000s 37.469us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 28.000s 24.426us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 33.000s 52.488us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 29.000s 45.736us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 31.000s 244.921us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 28.000s 24.426us 1 1 100.00
otbn_csr_aliasing 29.000s 45.736us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 66.000s 6471.442us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 42.000s 2327.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 18.000s 213.576us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 47.000s 752.042us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 97.000s 304.377us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 35.000s 723.310us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 30.000s 22.492us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.475us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 33.195us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 32.000s 16.463us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 23.000s 50.495us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 66.618us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 66.618us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 29.000s 37.469us 1 1 100.00
otbn_csr_rw 28.000s 24.426us 1 1 100.00
otbn_csr_aliasing 29.000s 45.736us 1 1 100.00
otbn_same_csr_outstanding 5.000s 96.653us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 29.000s 37.469us 1 1 100.00
otbn_csr_rw 28.000s 24.426us 1 1 100.00
otbn_csr_aliasing 29.000s 45.736us 1 1 100.00
otbn_same_csr_outstanding 5.000s 96.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 31.000s 90.656us 1 1 100.00
otbn_dmem_err 31.000s 34.230us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 34.000s 229.416us 1 1 100.00
otbn_controller_ispr_rdata_err 32.000s 115.508us 1 1 100.00
otbn_mac_bignum_acc_err 25.000s 185.464us 1 1 100.00
otbn_urnd_err 4.000s 26.421us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 26.000s 68.652us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 15.000s 14.050us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 24.819us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
otbn_tl_intg_err 10.000s 247.956us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 22.000s 310.855us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 55.004us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 31.000s 34.230us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 31.000s 90.656us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 247.956us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 30.000s 22.492us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 31.000s 90.656us 1 1 100.00
otbn_dmem_err 31.000s 34.230us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.475us 1 1 100.00
otbn_illegal_mem_acc 26.000s 68.652us 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 31.000s 90.656us 1 1 100.00
otbn_dmem_err 31.000s 34.230us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.475us 1 1 100.00
otbn_illegal_mem_acc 26.000s 68.652us 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 30.000s 22.492us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 31.000s 90.656us 1 1 100.00
otbn_dmem_err 31.000s 34.230us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.475us 1 1 100.00
otbn_illegal_mem_acc 26.000s 68.652us 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 30.000s 38.838us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 70.458us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 24.000s 73.178us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 24.000s 73.178us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 58.694us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 162.123us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 89.397us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 89.397us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 31.246us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 97.000s 304.377us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 14.000s 47.202us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 110.254us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 126.000s 2710.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 177.000s 1517.704us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 26.415us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 47635317572345627575185626279941985472019813346174689338381468735126982305020 271
UVM_INFO @ 1517703710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---