Simulation Results: otp_ctrl

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.48 %
  • code
  • 78.41 %
  • assert
  • 94.50 %
  • func
  • 71.53 %
  • line
  • 88.67 %
  • branch
  • 84.25 %
  • cond
  • 92.27 %
  • toggle
  • 81.03 %
  • FSM
  • 45.83 %
Validation stages
V1
88.89%
V2
85.00%
V2S
77.78%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.590s 58.870us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.830s 77.574us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.560s 151.793us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.130s 173.877us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.770s 180.580us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.360s 1027.628us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.560s 151.793us 1 1 100.00
otp_ctrl_csr_aliasing 4.770s 180.580us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.310s 566.850us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.500s 144.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 18.440s 3590.662us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.230s 312.345us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 13.170s 7178.675us 1 1 100.00
otp_ctrl_check_fail 2.490s 92.628us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.200s 604.897us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 34.350s 4766.790us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 17.900s 2033.955us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 15.440s 891.869us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 24.580s 4676.848us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 20.170s 1830.649us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 149.090s 115375.084us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.830s 40.909us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.860s 140.415us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.730s 921.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.730s 921.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.830s 77.574us 1 1 100.00
otp_ctrl_csr_rw 1.560s 151.793us 1 1 100.00
otp_ctrl_csr_aliasing 4.770s 180.580us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.120s 300.290us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.830s 77.574us 1 1 100.00
otp_ctrl_csr_rw 1.560s 151.793us 1 1 100.00
otp_ctrl_csr_aliasing 4.770s 180.580us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.120s 300.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
otp_ctrl_tl_intg_err 11.790s 1442.785us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.790s 1442.785us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_ctrl_macro_errs 24.580s 4676.848us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_ctrl_macro_errs 24.580s 4676.848us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.080s 508.833us 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.230s 312.345us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.490s 92.628us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 3.140s 188.159us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.920s 22335.401us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.200s 604.897us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.090s 1962.807us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 24.580s 4676.848us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 14.060s 7981.433us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 108.060s 5459.766us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 3 test runs
otp_ctrl_check_fail 83304129410982274206710433853090714497213428609834101679296538295626742528438 2355
UVM_INFO @ 92627905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 82915662686743962126690644514615744152428715636234746277296004532621356019977 13995
UVM_INFO @ 4676847606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 114408498680741777775078820267183496745634170967593907120586136180550730129784 121988
UVM_INFO @ 115375083690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 37693028206270594165837212248891622660918312646342543439686737165090001076439 98
UVM_INFO @ 1027627602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---