Simulation Results: pattgen

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 98.87 %
  • assert
  • 97.87 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 360.793us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 21.428us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 39.327us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 352.162us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 17.636us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 103.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 39.327us 1 1 100.00
pattgen_csr_aliasing 2.000s 17.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 3602.103s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 44.000s 2633.807us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 910.328us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 3.000s 198.298us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 13.633us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 13.210us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 86.085us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 86.085us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 21.428us 1 1 100.00
pattgen_csr_rw 1.000s 39.327us 1 1 100.00
pattgen_csr_aliasing 2.000s 17.636us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 109.602us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 21.428us 1 1 100.00
pattgen_csr_rw 1.000s 39.327us 1 1 100.00
pattgen_csr_aliasing 2.000s 17.636us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 109.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 171.158us 1 1 100.00
pattgen_sec_cm 1.000s 43.452us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 171.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
pattgen_stress_all_with_rand_reset 7.000s 1530.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 4.000s 424.311us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
pattgen_perf 74063161972445129618318910123633286690821079459523908069977939215187328426790 None