Simulation Results: pwrmgr

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.03 %
  • code
  • 91.30 %
  • assert
  • 98.43 %
  • func
  • 98.35 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.760s 27.619us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.630s 27.575us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 97.103us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.660s 347.115us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.770s 177.373us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.920s 40.253us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 97.103us 1 1 100.00
pwrmgr_csr_aliasing 0.770s 177.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.740s 87.629us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.740s 87.629us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.120s 81.516us 1 1 100.00
pwrmgr_lowpower_invalid 0.740s 51.154us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.790s 50.322us 1 1 100.00
pwrmgr_reset_invalid 0.790s 60.922us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.790s 50.322us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.770s 401.388us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.870s 111.597us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.770s 109.025us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.240s 2660.924us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.720s 32.292us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.470s 259.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.470s 259.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 27.575us 1 1 100.00
pwrmgr_csr_rw 0.630s 97.103us 1 1 100.00
pwrmgr_csr_aliasing 0.770s 177.373us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 66.324us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 27.575us 1 1 100.00
pwrmgr_csr_rw 0.630s 97.103us 1 1 100.00
pwrmgr_csr_aliasing 0.770s 177.373us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 66.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.150s 216.764us 1 1 100.00
pwrmgr_sec_cm 1.640s 642.386us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.640s 642.386us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.640s 642.386us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.150s 216.764us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.800s 1333.898us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.770s 401.388us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.880s 721.196us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.800s 50.766us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.690s 31.588us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.640s 642.386us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.640s 642.386us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.640s 642.386us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.610s 29.976us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.650s 55.608us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.940s 378.917us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 97.103us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 97.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.710s 226.437us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.220s 2860.376us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower 1 test run
pwrmgr_reset_invalid 3721167964600699902326966748198576616755668160603673911863339191023836762163 86
UVM_INFO @ 60921805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---