Simulation Results: rom_ctrl/32kb

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 95.71 %
  • assert
  • 97.68 %
  • func
  • 93.56 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.62 %
  • toggle
  • 95.52 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 181.690us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.660s 295.006us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.440s 126.845us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.130s 287.597us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.730s 169.948us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.210s 179.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.440s 126.845us 1 1 100.00
rom_ctrl_csr_aliasing 4.730s 169.948us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.430s 554.298us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.550s 417.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 568.161us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.480s 577.943us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.920s 308.567us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.500s 1914.809us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.360s 124.803us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.360s 124.803us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.660s 295.006us 1 1 100.00
rom_ctrl_csr_rw 3.440s 126.845us 1 1 100.00
rom_ctrl_csr_aliasing 4.730s 169.948us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.110s 347.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.660s 295.006us 1 1 100.00
rom_ctrl_csr_rw 3.440s 126.845us 1 1 100.00
rom_ctrl_csr_aliasing 4.730s 169.948us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.110s 347.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.390s 1911.112us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 102.110s 2721.578us 1 1 100.00
rom_ctrl_tl_intg_err 48.030s 439.370us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 102.110s 2721.578us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 102.110s 2721.578us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.110s 2721.578us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 102.110s 2721.578us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 181.690us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 181.690us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 181.690us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 48.030s 439.370us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
rom_ctrl_kmac_err_chk 7.920s 308.567us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.470s 15651.006us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.390s 1911.112us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.110s 2721.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 29.810s 1957.331us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 8231859054674271771367775030924608514052185918001328626919723132373101924226 79
UVM_INFO @ 568160728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---