Simulation Results: rom_ctrl/64kb

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.02 %
  • code
  • 98.52 %
  • assert
  • 97.68 %
  • func
  • 97.85 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.51 %
  • toggle
  • 94.98 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.640s 224.254us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 13.220s 208.553us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.550s 524.519us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.520s 541.149us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.060s 297.745us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.520s 330.765us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.550s 524.519us 1 1 100.00
rom_ctrl_csr_aliasing 7.060s 297.745us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.660s 383.397us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.500s 291.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.800s 247.828us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.580s 1118.872us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.690s 9908.710us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.220s 1027.633us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.460s 296.762us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.460s 296.762us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 13.220s 208.553us 1 1 100.00
rom_ctrl_csr_rw 5.550s 524.519us 1 1 100.00
rom_ctrl_csr_aliasing 7.060s 297.745us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.020s 212.526us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 13.220s 208.553us 1 1 100.00
rom_ctrl_csr_rw 5.550s 524.519us 1 1 100.00
rom_ctrl_csr_aliasing 7.060s 297.745us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.020s 212.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.560s 1628.075us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 457.870s 2848.505us 1 1 100.00
rom_ctrl_tl_intg_err 101.390s 696.784us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 457.870s 2848.505us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 457.870s 2848.505us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 457.870s 2848.505us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 457.870s 2848.505us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.640s 224.254us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.640s 224.254us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.640s 224.254us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 101.390s 696.784us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
rom_ctrl_kmac_err_chk 13.690s 9908.710us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 107.840s 2256.320us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.560s 1628.075us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 457.870s 2848.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 275.120s 9129.864us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 23622562789229681343889632214975946834427129991482886165703894437782123731073 79
UVM_INFO @ 247827619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---