Simulation Results: rstmgr

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.97 %
  • code
  • 99.35 %
  • assert
  • 98.53 %
  • func
  • 96.02 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.310s 262.247us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.950s 140.288us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.960s 68.291us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.250s 704.045us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.210s 421.278us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.300s 176.162us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.960s 68.291us 1 1 100.00
rstmgr_csr_aliasing 2.210s 421.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.110s 208.525us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.510s 645.374us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.900s 129.371us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.690s 2188.461us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.690s 2188.461us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.690s 2188.461us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.690s 2188.461us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.060s 4698.275us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.930s 75.077us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.430s 479.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.430s 479.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.950s 140.288us 1 1 100.00
rstmgr_csr_rw 0.960s 68.291us 1 1 100.00
rstmgr_csr_aliasing 2.210s 421.278us 1 1 100.00
rstmgr_same_csr_outstanding 1.360s 252.490us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.950s 140.288us 1 1 100.00
rstmgr_csr_rw 0.960s 68.291us 1 1 100.00
rstmgr_csr_aliasing 2.210s 421.278us 1 1 100.00
rstmgr_same_csr_outstanding 1.360s 252.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.250s 8806.677us 1 1 100.00
rstmgr_tl_intg_err 2.740s 929.588us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.250s 8806.677us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.250s 8806.677us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.740s 929.588us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.350s 193.375us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.520s 1394.496us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.150s 302.109us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.250s 8806.677us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.960s 68.291us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.960s 68.291us 1 1 100.00