Simulation Results: rv_timer

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.42 %
  • code
  • 100.00 %
  • assert
  • 98.73 %
  • func
  • 93.53 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.720s 452.684us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 26.169us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 15.959us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.710s 459.927us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 15.113us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 16.209us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 15.959us 1 1 100.00
rv_timer_csr_aliasing 0.770s 15.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.850s 90.712us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.860s 730.655us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 364.960s 1267789.267us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 364.960s 1267789.267us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.810s 1446.530us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 38.460us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 76.791us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.820s 46.319us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.820s 46.319us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 26.169us 1 1 100.00
rv_timer_csr_rw 0.550s 15.959us 1 1 100.00
rv_timer_csr_aliasing 0.770s 15.113us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 129.172us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 26.169us 1 1 100.00
rv_timer_csr_rw 0.550s 15.959us 1 1 100.00
rv_timer_csr_aliasing 0.770s 15.113us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 129.172us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.780s 1291.607us 1 1 100.00
rv_timer_tl_intg_err 1.170s 125.562us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.170s 125.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.890s 64.926us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.570s 48.535us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 14.210s 10842.525us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 68706304196957835951881830824928128465559088479749242159643705825641598588362 77
UVM_INFO @ 64925733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 82310566846764947430568059465248412960766098364105102210376281681602537808734 76
UVM_INFO @ 90712085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 12824794783989507690057079508374299530753996571875571898421287962061822506714 75
UVM_INFO @ 48535176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---