Simulation Results: sram_ctrl/main

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.83 %
  • code
  • 96.01 %
  • assert
  • 97.69 %
  • func
  • 93.80 %
  • block
  • 95.09 %
  • line
  • 95.72 %
  • branch
  • 92.23 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 7746.421us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 77.437us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.340us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 116.231us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 703.479us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 20.340us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.705us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 220.000s 32973.947us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 50.000s 2608.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 35.000s 48543.687us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 140.000s 4576.795us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 148.000s 15343.869us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 38.000s 10171.874us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 13.000s 4474.826us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 16.000s 13679.934us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1390.716us 1 1 100.00
sram_ctrl_partial_access_b2b 180.000s 15082.945us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 5.000s 1348.068us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 703.813us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 2550.987us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2018.789us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1396.442us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 162.000s 44106.567us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 153.972us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 146.827us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 146.827us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 77.437us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.340us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.705us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.949us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 77.437us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.340us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 21.705us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 7867.169us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 199.994us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 315.887us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 199.994us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 315.887us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2018.789us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2018.789us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.340us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 16.000s 13679.934us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 13679.934us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 13679.934us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 13.000s 4474.826us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 2905.283us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 7867.169us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 3500.073us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 7746.421us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 7746.421us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 16.000s 13679.934us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 199.994us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 13.000s 4474.826us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 199.994us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 199.994us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 7746.421us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 199.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 14.000s 1154.480us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 60274275638161857027955423602541021243397476542695268435947066772835996372570 86
UVM_INFO @ 1348068320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 106765506328262475352255580510372904161453328399367213748655046682184524514462 86
UVM_INFO @ 703813480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 84343472398939898865499249000444098007082251742614498371356738683144750849845 86
UVM_INFO @ 2550987324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---