Simulation Results: sram_ctrl/ret

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.00 %
  • code
  • 83.31 %
  • assert
  • 98.08 %
  • func
  • 94.60 %
  • block
  • 93.83 %
  • line
  • 94.99 %
  • branch
  • 89.51 %
  • toggle
  • 82.08 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 35.758us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 34.931us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.198us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 185.085us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.774us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 233.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.198us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.774us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 2803.691us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 115.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 4.000s 681.668us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 118.000s 9601.010us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 487.099us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 1058.980us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 385.445us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1009.806us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 197.192us 1 1 100.00
sram_ctrl_partial_access_b2b 318.000s 460197.901us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 102.763us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 52.082us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 30.592us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 119.563us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 197.327us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 33.000s 13610.228us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.495us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 72.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 72.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 34.931us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.198us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.774us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 46.152us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 34.931us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.198us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.774us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 46.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 259.455us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1214.356us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 157.241us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1214.356us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 157.241us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 119.563us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 119.563us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.198us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1009.806us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1009.806us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1009.806us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 385.445us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 40.037us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 259.455us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 130.517us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 35.758us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 35.758us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1009.806us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1214.356us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 385.445us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1214.356us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1214.356us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 35.758us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1214.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 38.000s 7700.201us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 56076900986145529993338503032907892762414752522038967252781762796041563796337 86
UVM_INFO @ 102763175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 86401238983000714046272020325696344432498091614292679876855939807305451415484 86
UVM_INFO @ 52082362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 41390176665969721907371455104623629313812014382841182905833801199618364317021 86
UVM_INFO @ 30592033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---