Simulation Results: sysrst_ctrl

 
16/06/2026 15:30:34 DVSim: v1.49.9 sha: 13a8919 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.35 %
  • code
  • 92.59 %
  • assert
  • 94.06 %
  • func
  • 66.40 %
  • line
  • 97.23 %
  • branch
  • 97.40 %
  • cond
  • 95.05 %
  • toggle
  • 99.54 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.050s 2111.533us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.200s 2480.298us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.760s 2395.393us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.480s 2555.445us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.720s 6096.480us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.030s 2037.856us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 63.410s 34544.824us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.230s 2652.568us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.570s 2070.788us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.030s 2037.856us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.230s 2652.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 181.590s 116514.377us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 50.810s 59879.604us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.480s 3499.660us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.630s 3689.322us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.930s 2530.792us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.410s 2046.003us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.530s 3629.884us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.190s 2609.278us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.220s 2825.460us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 61.700s 38582.109us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 510.870s 1302950.281us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.270s 2042.518us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.450s 2014.353us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.040s 2239.644us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.040s 2239.644us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.720s 6096.480us 1 1 100.00
sysrst_ctrl_csr_rw 4.030s 2037.856us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.230s 2652.568us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.540s 8132.689us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.720s 6096.480us 1 1 100.00
sysrst_ctrl_csr_rw 4.030s 2037.856us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.230s 2652.568us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.540s 8132.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 40.230s 22012.132us 1 1 100.00
sysrst_ctrl_tl_intg_err 20.180s 42848.672us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 20.180s 42848.672us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.270s 3277.567us 1 1 100.00