Simulation Results: adc_ctrl

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.94 %
  • code
  • 92.79 %
  • assert
  • 92.06 %
  • func
  • 12.97 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.10 %
  • toggle
  • 99.76 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.340s 6028.436us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.840s 633.323us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.380s 519.518us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 3.560s 1196.367us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.980s 543.043us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.880s 724.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.380s 519.518us 1 1 100.00
adc_ctrl_csr_aliasing 1.980s 543.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.750s 437.313us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.680s 279.985us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.730s 302.520us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.830s 411.239us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.880s 394.500us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.760s 409.283us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.130s 305.860us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.990s 315.573us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.960s 3725.850us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 41.860s 30884.059us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 41.020s 99692.843us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.230s 806.174us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.780s 553.264us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.790s 450.093us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.100s 381.182us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.100s 381.182us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.840s 633.323us 1 1 100.00
adc_ctrl_csr_rw 1.380s 519.518us 1 1 100.00
adc_ctrl_csr_aliasing 1.980s 543.043us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.750s 2705.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.840s 633.323us 1 1 100.00
adc_ctrl_csr_rw 1.380s 519.518us 1 1 100.00
adc_ctrl_csr_aliasing 1.980s 543.043us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.750s 2705.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 5.070s 3500.152us 1 1 100.00
adc_ctrl_tl_intg_err 6.660s 4009.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.660s 4009.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.320s 701.001us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 106238618323802570642235954974127972374227916973596309699887257602307128308148 386
UVM_INFO @ 437313284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 93345595554939650042781393821077058536402074259889585664616056235597911704916 386
UVM_INFO @ 279985415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 32695466160456340650291397767248319383904316290785624486600548873878685290546 386
UVM_INFO @ 302520442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 66711354331346894667946736708712268951694321820271658528289338762242403195751 386
UVM_INFO @ 411239417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 14608762374664076950751671116919984431959079023931821789384898042142001956 386
UVM_INFO @ 394500299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 104498357711686464448847678043964920582032604074037429086902461972735017939337 386
UVM_INFO @ 409282877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 58268902712432559910845011229308255840137464683914270663474223843873603250591 386
UVM_INFO @ 315572734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 66222445463611206571265841092381966934880251936756275709860301766749409548653 386
UVM_INFO @ 305859972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 80077838485230732493622122925857770478897795555506868731712240046389305366158 399
UVM_INFO @ 701001434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 37678712354618506215518632785832861848186622335076286880466987310886908820608 387
UVM_INFO @ 806174263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---