Simulation Results: aes/masked

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.06 %
  • code
  • 93.49 %
  • assert
  • 98.23 %
  • func
  • 72.47 %
  • block
  • 94.10 %
  • line
  • 95.80 %
  • branch
  • 86.84 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 120.370us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 58.881us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 3.000s 66.737us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 78.779us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 470.077us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 79.224us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 52.810us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 78.779us 1 1 100.00
aes_csr_aliasing 3.000s 79.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 58.881us 1 1 100.00
aes_config_error 3.000s 95.985us 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 58.881us 1 1 100.00
aes_config_error 3.000s 95.985us 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
back2back 2 2 100.00
aes_stress 6.000s 474.569us 1 1 100.00
aes_b2b 8.000s 226.857us 1 1 100.00
backpressure 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 58.881us 1 1 100.00
aes_config_error 3.000s 95.985us 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
aes_alert_reset 4.000s 249.968us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 96.595us 1 1 100.00
aes_config_error 3.000s 95.985us 1 1 100.00
aes_alert_reset 4.000s 249.968us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 159.522us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 37.000s 27563.633us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 249.968us 1 1 100.00
stress 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
sideload 2 2 100.00
aes_stress 6.000s 474.569us 1 1 100.00
aes_sideload 3.000s 446.928us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 116.183us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10.000s 330.600us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 3.000s 63.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 656.493us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 656.493us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 3.000s 66.737us 1 1 100.00
aes_csr_rw 2.000s 78.779us 1 1 100.00
aes_csr_aliasing 3.000s 79.224us 1 1 100.00
aes_same_csr_outstanding 2.000s 145.699us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 3.000s 66.737us 1 1 100.00
aes_csr_rw 2.000s 78.779us 1 1 100.00
aes_csr_aliasing 3.000s 79.224us 1 1 100.00
aes_same_csr_outstanding 2.000s 145.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 81.990us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 332.829us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 903.161us 1 1 100.00
aes_tl_intg_err 3.000s 156.773us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 156.773us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 249.968us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 58.881us 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
aes_alert_reset 4.000s 249.968us 1 1 100.00
aes_core_fi 4.000s 674.743us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 95.985us 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
aes_core_fi 4.000s 674.743us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 72.755us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 183.323us 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 6.000s 474.569us 1 1 100.00
aes_sideload 3.000s 446.928us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 183.323us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 183.323us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 183.323us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 183.323us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 183.323us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 6.000s 474.569us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 16.000s 1302.910us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
aes_ctr_fi 2.000s 96.890us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 16.000s 1302.910us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 16.000s 1302.910us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_ctr_fi 2.000s 96.890us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 16.000s 1302.910us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
aes_ctr_fi 2.000s 96.890us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 249.968us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
aes_ctr_fi 2.000s 96.890us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
aes_ctr_fi 2.000s 96.890us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_ctr_fi 2.000s 96.890us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 16.000s 1302.910us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 16.000s 1302.910us 0 1 0.00
aes_control_fi 42.000s 10006.047us 0 1 0.00
aes_cipher_fi 3.000s 52.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 559.572us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 47003013924597766917141372387077230992061637772951346156292377290197785553080 3765
UVM_INFO @ 81989783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 30423580845505723173960459320005805697527959128050301398434018161957262711800 13838
UVM_INFO @ 330599987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 77536085505041220229322286473268636686081832222082413386163580564236161494920 1002
UVM_INFO @ 559572036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 34427047570356787375940029731622800049390849520717191840913216394611985549272 89445
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 38729081812376533576322509868165112200451999136845726726021423588978469215360 155
UVM_INFO @ 10006046933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---