Simulation Results: aes/unmasked

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.04 %
  • code
  • 89.92 %
  • assert
  • 97.92 %
  • func
  • 76.29 %
  • block
  • 89.92 %
  • line
  • 92.18 %
  • branch
  • 80.62 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 95.406us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 72.877us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 53.435us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 57.908us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 154.773us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 221.988us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 206.496us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 57.908us 1 1 100.00
aes_csr_aliasing 3.000s 221.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 72.877us 1 1 100.00
aes_config_error 2.000s 66.759us 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 72.877us 1 1 100.00
aes_config_error 2.000s 66.759us 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 97.862us 1 1 100.00
aes_b2b 6.000s 133.062us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 72.877us 1 1 100.00
aes_config_error 2.000s 66.759us 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
aes_alert_reset 3.000s 78.539us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 68.561us 1 1 100.00
aes_config_error 2.000s 66.759us 1 1 100.00
aes_alert_reset 3.000s 78.539us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 287.007us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 210.506us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 78.539us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 97.862us 1 1 100.00
aes_sideload 4.000s 102.626us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 65.728us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 11.000s 384.489us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 96.418us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 265.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 265.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.435us 1 1 100.00
aes_csr_rw 3.000s 57.908us 1 1 100.00
aes_csr_aliasing 3.000s 221.988us 1 1 100.00
aes_same_csr_outstanding 8.000s 180.777us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.435us 1 1 100.00
aes_csr_rw 3.000s 57.908us 1 1 100.00
aes_csr_aliasing 3.000s 221.988us 1 1 100.00
aes_same_csr_outstanding 8.000s 180.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 167.864us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 113.792us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 820.562us 1 1 100.00
aes_tl_intg_err 2.000s 281.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 281.451us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 78.539us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 72.877us 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
aes_alert_reset 3.000s 78.539us 1 1 100.00
aes_core_fi 3.000s 475.442us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 66.759us 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
aes_core_fi 3.000s 475.442us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 184.610us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 61.634us 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 97.862us 1 1 100.00
aes_sideload 4.000s 102.626us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 61.634us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 61.634us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 61.634us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 61.634us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 61.634us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 97.862us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 92.628us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
aes_ctr_fi 2.000s 70.826us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 92.628us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 92.628us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_ctr_fi 2.000s 70.826us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 92.628us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
aes_ctr_fi 2.000s 70.826us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 78.539us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
aes_ctr_fi 2.000s 70.826us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
aes_ctr_fi 2.000s 70.826us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_ctr_fi 2.000s 70.826us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 92.628us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 92.628us 0 1 0.00
aes_control_fi 2.000s 118.393us 1 1 100.00
aes_cipher_fi 1.000s 69.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 32.265us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 1404097977623543300284252490707165567210692943346805258320320732899366260762 5843
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 32659488075282838325971979487931022659808052090586847689894654917092861628079 163
UVM_INFO @ 32265017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---