Simulation Results

Simulation Results: chip

17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
73.91 %

code
83.88 %

assert
97.37 %

func
40.47 %

line
94.04 %

branch
92.30 %

cond
87.42 %

toggle
88.49 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		75.99%
V2S		50.00%
V3		61.54%
unmapped		63.64%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	211.810s	3165.278us	1	1	100.00
	chip_sw_example_rom	94.560s	2955.535us	1	1	100.00
	chip_sw_example_manufacturer	114.270s	2666.250us	1	1	100.00
	chip_sw_example_concurrency	130.560s	2984.423us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	189.040s	3990.583us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	333.990s	5601.192us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	676.820s	7675.189us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	5536.880s	38933.094us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	314.570s	5830.448us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	5536.880s	38933.094us	1	1	100.00
	chip_csr_rw	333.990s	5601.192us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.380s	51.138us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	309.470s	4272.044us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	309.470s	4272.044us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	309.470s	4272.044us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	342.470s	4149.107us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	342.470s	4149.107us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	357.300s	4323.101us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	375.810s	4318.089us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	399.960s	4491.942us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	384.220s	4111.877us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	451.570s	4619.016us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	617.080s	8402.736us	1	1	100.00

212/279 passed

75.99 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	190.740s	5781.752us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	190.740s	5781.752us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	192.690s	3755.458us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	235.400s	6292.744us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	157.010s	3353.098us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	437.050s	7063.774us	1	1	100.00
	chip_tap_straps_testunlock0	96.950s	2886.198us	1	1	100.00
	chip_tap_straps_rma	389.500s	6547.650us	1	1	100.00
	chip_tap_straps_prod	1325.840s	19328.943us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	178.350s	3393.499us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	826.090s	9014.194us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	373.090s	6094.692us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	373.090s	6094.692us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	569.890s	8196.824us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1041.270s	11728.871us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	361.780s	4576.242us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	580.500s	6234.591us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3993.530s	18883.934us	1	1	100.00
	chip_sw_aes_enc_jitter_en	188.830s	3280.867us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	571.110s	6584.245us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	171.540s	2917.243us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	876.900s	8046.262us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	229.370s	3117.239us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	383.250s	5381.208us	1	1	100.00
	chip_sw_clkmgr_jitter	123.680s	2527.196us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	227.890s	3247.034us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	361.440s	5605.128us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	236.880s	4706.904us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	178.800s	3311.304us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	236.880s	4706.904us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	150.260s	2964.597us	1	1	100.00
	chip_sw_aes_smoketest	153.930s	2744.787us	1	1	100.00
	chip_sw_aon_timer_smoketest	180.620s	2902.820us	1	1	100.00
	chip_sw_clkmgr_smoketest	154.170s	3191.972us	1	1	100.00
	chip_sw_csrng_smoketest	155.060s	2600.477us	1	1	100.00
	chip_sw_entropy_src_smoketest	777.850s	6240.739us	1	1	100.00
	chip_sw_gpio_smoketest	216.040s	3405.309us	1	1	100.00
	chip_sw_hmac_smoketest	217.190s	3230.419us	1	1	100.00
	chip_sw_kmac_smoketest	195.330s	3699.905us	1	1	100.00
	chip_sw_otbn_smoketest	880.540s	7655.193us	1	1	100.00
	chip_sw_pwrmgr_smoketest	351.740s	6326.189us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	290.770s	5986.060us	1	1	100.00
	chip_sw_rv_plic_smoketest	140.110s	2582.787us	1	1	100.00
	chip_sw_rv_timer_smoketest	161.530s	3652.567us	1	1	100.00
	chip_sw_rstmgr_smoketest	160.780s	3413.702us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	138.110s	2769.660us	1	1	100.00
	chip_sw_uart_smoketest	176.730s	3017.405us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	147.730s	3105.590us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	357.330s	5242.505us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8384.250s	62662.512us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3282.470s	15843.609us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	105.524s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	191.990s	3395.511us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	156.440s	3370.430us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7393.950s	54260.775us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7801.110s	57900.598us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	76.960s	2679.104us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	76.960s	2679.104us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	5536.880s	38933.094us	1	1	100.00
	chip_same_csr_outstanding	1229.980s	16232.787us	1	1	100.00
	chip_csr_hw_reset	189.040s	3990.583us	1	1	100.00
	chip_csr_rw	333.990s	5601.192us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	5536.880s	38933.094us	1	1	100.00
	chip_same_csr_outstanding	1229.980s	16232.787us	1	1	100.00
	chip_csr_hw_reset	189.040s	3990.583us	1	1	100.00
	chip_csr_rw	333.990s	5601.192us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	31.220s	628.761us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	6.430s	53.585us	1	1	100.00
	xbar_smoke_large_delays	47.350s	8420.401us	1	1	100.00
	xbar_smoke_slow_rsp	48.340s	5294.177us	1	1	100.00
	xbar_random_zero_delays	34.200s	610.129us	1	1	100.00
	xbar_random_large_delays	21.440s	3332.571us	1	1	100.00
	xbar_random_slow_rsp	166.210s	17749.014us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	23.270s	205.515us	1	1	100.00
	xbar_error_and_unmapped_addr	34.950s	1455.724us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	39.190s	1708.350us	1	1	100.00
	xbar_error_and_unmapped_addr	34.950s	1455.724us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	30.590s	675.410us	1	1	100.00
	xbar_access_same_device_slow_rsp	697.790s	83267.616us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	24.550s	1150.768us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	56.080s	1674.222us	1	1	100.00
	xbar_stress_all_with_error	79.110s	1651.774us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	286.130s	3438.286us	1	1	100.00
	xbar_stress_all_with_reset_error	170.090s	754.155us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3282.470s	15843.609us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2553.490s	26582.165us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3106.480s	15412.714us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	59.836s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	15.634s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	43.987s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	23.765s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	54.786s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	129.753s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.625s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	7.557s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	59.137s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	44.578s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	62.805s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	86.978s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	91.516s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	47.511s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	63.086s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.100s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	22.710s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	22.870s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.850s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	20.390s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	24.570s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.450s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.060s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.170s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	23.310s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	23.060s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.310s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	20.770s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	22.770s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.110s	10.160us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	131.116s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	71.424s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	9.926s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	65.680s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	64.687s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	6099.120s	28842.488us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3160.370s	16714.493us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5911.180s	29668.893us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3295.500s	15997.612us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3420.180s	34631.059us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3420.180s	34631.059us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	186.710s	3251.607us	1	1	100.00
	chip_sw_aes_enc_jitter_en	188.830s	3280.867us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	155.000s	3289.286us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	168.310s	3254.069us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1712.310s	12025.435us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	198.360s	3128.394us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	404.010s	6002.404us	1	1	100.00
chip_sw_all_escalation_resets				0	1	0.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	572.130s	5274.989us	1	1	100.00
	chip_plic_all_irqs_10	297.360s	3304.380us	1	1	100.00
	chip_plic_all_irqs_20	458.010s	4739.203us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	214.800s	3134.655us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1216.050s	13472.462us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	377.660s	6009.374us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	130.620s	2561.722us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.142s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1171.570s	9021.811us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1067.530s	8532.934us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	777.940s	8241.372us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8933.760s	255621.427us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	232.240s	3565.177us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	351.740s	6326.189us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	232.240s	3565.177us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	708.010s	9033.643us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	708.010s	9033.643us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	376.600s	8695.598us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	394.590s	6006.048us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	608.950s	5594.554us	1	1	100.00
	chip_sw_aes_idle	168.310s	3254.069us	1	1	100.00
	chip_sw_hmac_enc_idle	187.420s	2918.926us	1	1	100.00
	chip_sw_kmac_idle	179.750s	3198.677us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	215.490s	4096.870us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	216.130s	4681.324us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	298.160s	4460.350us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	333.700s	4702.491us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	793.120s	12329.452us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	417.610s	4510.940us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	442.070s	5282.101us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	427.150s	4407.651us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	391.480s	4654.152us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	416.570s	4753.413us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	410.390s	4597.462us	1	1	100.00
	chip_sw_ast_clk_outputs	569.890s	8196.824us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	758.170s	14596.865us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	427.150s	4407.651us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	391.480s	4654.152us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	361.780s	4576.242us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	580.500s	6234.591us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3993.530s	18883.934us	1	1	100.00
	chip_sw_aes_enc_jitter_en	188.830s	3280.867us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	571.110s	6584.245us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	171.540s	2917.243us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	876.900s	8046.262us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	229.370s	3117.239us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	383.250s	5381.208us	1	1	100.00
	chip_sw_clkmgr_jitter	123.680s	2527.196us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	140.080s	3105.828us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	426.010s	5069.733us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	656.930s	7408.493us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4159.410s	25590.533us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	150.340s	2987.537us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	148.540s	3218.886us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	641.770s	8003.625us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	178.720s	3899.114us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	440.790s	6170.470us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1181.710s	22253.232us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2408.200s	18475.329us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	569.890s	8196.824us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	338.930s	4691.043us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	259.750s	3588.984us	1	1	100.00
chip_sw_clkmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1171.570s	9021.811us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2225.090s	24694.554us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	169.970s	3516.688us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	499.560s	8217.477us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	190.720s	2899.774us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	5433.250s	30638.078us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	186.280s	3198.079us	1	1	100.00
	chip_sw_edn_entropy_reqs	626.050s	6201.841us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	186.280s	3198.079us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2225.090s	24694.554us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	198.170s	3324.239us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1190.350s	16462.735us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	568.010s	5015.753us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	580.500s	6234.591us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	321.820s	3876.633us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	361.780s	4576.242us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3379.790s	44006.631us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1190.350s	16462.735us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	261.940s	3587.199us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1200.710s	9876.123us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.910s	2941.126us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3379.790s	44006.631us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.910s	2941.126us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.910s	2941.126us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.910s	2941.126us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.910s	2941.126us	0	1	0.00
chip_sw_flash_lc_escalate_en				0	1	0.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	137.980s	4945.247us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	573.840s	5489.609us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	484.890s	5463.303us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	484.890s	5463.303us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	190.240s	3084.973us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	171.540s	2917.243us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	187.420s	2918.926us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1534.470s	12026.795us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1813.600s	12018.523us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	355.900s	4442.406us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	518.620s	6022.132us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	455.180s	5198.257us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	285.150s	4445.375us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1200.710s	9876.123us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	876.900s	8046.262us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1124.340s	10241.539us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1712.310s	12025.435us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4330.720s	20026.706us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	158.750s	3010.149us	1	1	100.00
	chip_sw_kmac_mode_kmac	184.900s	3129.744us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	229.370s	3117.239us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1200.710s	9876.123us	1	1	100.00
chip_sw_kmac_app_lc				0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	138.950s	3006.934us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1245.340s	8810.492us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	179.750s	3198.677us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	404.010s	6002.404us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	437.050s	7063.774us	1	1	100.00
	chip_tap_straps_rma	389.500s	6547.650us	1	1	100.00
	chip_tap_straps_prod	1325.840s	19328.943us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	172.930s	2570.304us	1	1	100.00
chip_sw_lc_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
chip_sw_lc_ctrl_transitions				0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
chip_sw_lc_ctrl_kmac_req				0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1221.770s	11016.952us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	22	81.82
	chip_sw_flash_ctrl_lc_rw_en	152.910s	2941.126us	0	1	0.00
	chip_sw_flash_rma_unlocked	3379.790s	44006.631us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	222.190s	3186.396us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	581.860s	8110.829us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	627.230s	7187.273us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	582.920s	8077.658us	0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
	chip_sw_keymgr_key_derivation	1200.710s	9876.123us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	322.990s	9707.487us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	619.420s	9642.291us	1	1	100.00
	chip_prim_tl_access	137.980s	4945.247us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	758.170s	14596.865us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	417.610s	4510.940us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	442.070s	5282.101us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	427.150s	4407.651us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	391.480s	4654.152us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	416.570s	4753.413us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	410.390s	4597.462us	1	1	100.00
	chip_tap_straps_dev	437.050s	7063.774us	1	1	100.00
	chip_tap_straps_rma	389.500s	6547.650us	1	1	100.00
	chip_tap_straps_prod	1325.840s	19328.943us	1	1	100.00
	chip_rv_dm_lc_disabled	187.690s	7504.198us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	183.760s	3805.850us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	101.240s	3346.569us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	84.360s	3665.943us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	228.510s	4013.389us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1327.950s	23888.264us	1	1	100.00
	chip_rv_dm_lc_disabled	187.690s	7504.198us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	602.410s	9794.449us	0	1	0.00
	chip_sw_lc_walkthrough_prod	715.860s	11616.798us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	596.940s	9554.588us	1	1	100.00
	chip_sw_lc_walkthrough_rma	331.660s	5900.073us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1327.950s	23888.264us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	71.450s	2354.277us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	66.520s	2475.885us	1	1	100.00
	rom_volatile_raw_unlock	125.592s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3917.530s	17466.078us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3993.530s	18883.934us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	608.950s	5594.554us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	608.950s	5594.554us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	608.950s	5594.554us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	282.830s	3029.997us	1	1	100.00
chip_otp_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1190.350s	16462.735us	1	1	100.00
	chip_sw_otbn_mem_scramble	282.830s	3029.997us	1	1	100.00
	chip_sw_keymgr_key_derivation	1200.710s	9876.123us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	459.130s	5231.204us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	136.640s	3011.572us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1190.350s	16462.735us	1	1	100.00
	chip_sw_otbn_mem_scramble	282.830s	3029.997us	1	1	100.00
	chip_sw_keymgr_key_derivation	1200.710s	9876.123us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	459.130s	5231.204us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	136.640s	3011.572us	1	1	100.00
chip_sw_otp_ctrl_program				0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	393.080s	4982.744us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	172.930s	2570.304us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	6	66.67
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	222.190s	3186.396us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	581.860s	8110.829us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	627.230s	7187.273us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	582.920s	8077.658us	0	1	0.00
	chip_sw_lc_ctrl_transition	880.970s	26562.987us	0	1	0.00
	chip_prim_tl_access	137.980s	4945.247us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	137.980s	4945.247us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	776.020s	7438.916us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	199.100s	5918.391us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	751.090s	23927.719us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	246.700s	7461.494us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	308.870s	7598.900us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	474.840s	6660.043us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	837.130s	23742.667us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1053.180s	15503.072us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	708.010s	9033.643us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	802.140s	11372.284us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	295.130s	4201.129us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	199.100s	5918.391us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	246.330s	3626.828us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1466.330s	25373.488us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	385.360s	7305.373us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	181.430s	3689.361us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	605.560s	13486.025us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	849.650s	9000.217us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	943.280s	12902.341us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1432.270s	27200.937us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	185.100s	3049.752us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	322.990s	9707.487us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	322.990s	9707.487us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	943.280s	12902.341us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	605.560s	13486.025us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	295.130s	4201.129us	1	1	100.00
	chip_sw_pwrmgr_smoketest	351.740s	6326.189us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	286.310s	4785.366us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	480.720s	5945.067us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	246.320s	3581.485us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1216.050s	13472.462us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	143.010s	2516.882us	1	1	100.00
chip_sw_rstmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1067.530s	8532.934us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	474.340s	5279.035us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	482.890s	5354.810us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	180.410s	2849.273us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	136.640s	3011.572us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	480.720s	5945.067us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	480.720s	5945.067us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	139.130s	2851.749us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	660.140s	10355.787us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	806.530s	13725.099us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	286.310s	4785.366us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	219.880s	3801.069us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	275.440s	5818.597us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	389.500s	6547.650us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	187.690s	7504.198us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	572.130s	5274.989us	1	1	100.00
	chip_plic_all_irqs_10	297.360s	3304.380us	1	1	100.00
	chip_plic_all_irqs_20	458.010s	4739.203us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	157.310s	2886.377us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	159.010s	3249.025us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3282.470s	15843.609us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	227.170s	4006.877us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	242.920s	3744.812us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	219.990s	3825.584us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	222.370s	3730.604us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	459.130s	5231.204us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	383.250s	5381.208us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	367.920s	7077.536us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	512.450s	8389.127us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	619.420s	9642.291us	1	1	100.00
chip_sw_sram_lc_escalation				1	2	50.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
	chip_sw_data_integrity_escalation	373.090s	6094.692us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	849.650s	9000.217us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	897.200s	23126.126us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	175.240s	3248.623us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	210.110s	3271.815us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	377.390s	5038.609us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	897.200s	23126.126us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	897.200s	23126.126us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2394.290s	20222.636us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2394.290s	20222.636us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	365.320s	6290.374us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3420.180s	34631.059us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	135.070s	3009.783us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	182.220s	3372.667us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	268.240s	3507.628us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	341.770s	4143.248us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	935.750s	8641.792us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5304.710s	31555.143us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1933.240s	12879.073us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	216.710s	3272.950us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	137.740s	2579.360us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	89.870s	2697.324us	0	1	0.00

16/26 passed

61.54 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10573.510s	70942.933us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1138.030s	6553.994us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	428.210s	6118.580us	0	1	0.00
	rom_e2e_jtag_debug_dev	472.660s	7608.090us	0	1	0.00
	rom_e2e_jtag_debug_rma	191.760s	3099.687us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	59.590s	2706.112us	0	1	0.00
	rom_e2e_jtag_inject_dev	61.950s	1942.915us	0	1	0.00
	rom_e2e_jtag_inject_rma	82.240s	2309.890us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	154.308s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	338.520s	4007.761us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	328.870s	3321.289us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	479.200s	3897.098us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	871.730s	6713.261us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	216.310s	2921.884us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	617.300s	5922.387us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	61.790s	2152.314us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	181.710s	2987.490us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	281.740s	4747.834us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	263.880s	4572.529us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	943.280s	12902.341us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	428.210s	6118.580us	0	1	0.00
	rom_e2e_jtag_debug_dev	472.660s	7608.090us	0	1	0.00
	rom_e2e_jtag_debug_rma	191.760s	3099.687us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	344.110s	5325.382us	1	1	100.00
chip_sw_plic_alerts				0	1	0.00
	chip_sw_all_escalation_resets	183.510s	3563.544us	0	1	0.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5767.460s	38146.328us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5767.460s	38146.328us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	185.190s	3017.396us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	342.470s	4149.107us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3279.410s	18458.480us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	204.740s	3739.413us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	19.700s	10.200us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	7.790s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	170.080s	3219.928us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	199.400s	3742.005us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	275.680s	4646.249us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	7.691s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	239.430s	3383.715us	1	1	100.00
	ate_bootstrap_flash_erase	541.970s	10010.400us	0	1	0.00
	ate_bootstrap_one_frame	6542.010s	45102.389us	1	1	100.00
	ate_bootstrap_disjoint	10217.930s	83904.722us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	97958228471927038554068888804776179457905404451010227120412957349865616989522	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	87911053736547120273195168805584958111841881029431094427661927088979389613014	None	Another command (pid=447731) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=410630) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=419819) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	97913500724663233963501067087271816799234772747159419133771369883794578043019	None	---- STDERR ---- Another command (pid=564362) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=465669) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	92154737287821904814543923707832417762238088990631244833998804381108390909114	None	Another command (pid=600937) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=630488) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=633148) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	22099350391547012229002017910613561230794788872058921200468660198091225024147	None	Another command (pid=467896) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=598026) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=593517) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	66488938506716662845781618621514209752734404055058864018037386677304879256342	None	Another command (pid=658722) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=677159) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=647756) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	37582093047703210652226171279218956302084550683487291559663482755567198380991	None	Another command (pid=467418) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=562549) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=562995) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	65421080372727638246481783834314126553946874586147153528009336064227123559384	None	Another command (pid=467896) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=598026) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=593517) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	39660091240007782883573175000832480675610812165264532761148948867643509123346	None	---- STDERR ---- Another command (pid=503348) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	62613649773562163516750587503295703121825401419564678869198757436139789866768	None	Another command (pid=634999) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=658722) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=647756) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	83498754000069433214494945526957284871954233543156430125074587728226442473701	None	Another command (pid=608532) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=630488) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=607542) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	98537656552960072054209339037126211263678746062419417643790411911176520180301	None	---- STDERR ---- Another command (pid=430421) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	54785364080815007169865103524377566624664824344330226748975320064655390575290	None	Another command (pid=423186) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=561392) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=467896) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	28077953243680381198063820864260406582239172607262342808790931880870142775637	None	---- STDERR ---- Another command (pid=611700) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=464873) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	89366117632391698100113125731717347290379592355568492148536944856375846503503	None	---- STDERR ---- Another command (pid=472415) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	35468894206987396402414852197121551240869723901507493644836004093471186303067	None	Another command (pid=378016) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=588783) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=587579) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	19386797728425827746376370785358774968263186245143598236932372629941053938104	None	Another command (pid=472415) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=559274) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=460932) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	109373526685370998334053904121911004175688092933043795123016156700796425027965	None	Another command (pid=414782) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=428119) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=465275) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	36627853245231524485707157317269266820795173055917034495521939809073852326453	None	Another command (pid=450873) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=461839) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=428119) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	68187486980309323949626190269653905592350504527725214230583619469228596957785	None	---- STDERR ---- Another command (pid=465275) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=500406) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	13595394980970369799414007987588772715204491762447795989908589847909826570593	None	Another command (pid=500406) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=381642) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=460932) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	66635322275550541510607075257446799223813948967935280721145314222234178733901	None	Another command (pid=430567) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=561392) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=467896) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	36834818436605828433993909105853265791880074976591640355217399002246275542234	None	Another command (pid=465275) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=500406) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=381642) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	60542565754506906949440867799826614872441640252882930944574022964894088174265	None	Another command (pid=611358) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=464873) is running. Waiting for it to complete on the server (server_pid=271457)... Another command (pid=560535) is running. Waiting for it to complete on the server (server_pid=271457)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	71650583443390589695131703366724448561546796134107248336293922092293325995171	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	54259705860827654426102235990105240606496823659688054710692123026359019407580	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	40120549723065231363491577364490942621742934293165146756155725358209506313852	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	55292408363988765267345239479344845143553833142822226818733063983608617404407	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	93795017894289627870325505821634789825955448862898684132626389075239332859114	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	62765129973046968436412335579874452041156218020027265015813421074696539564955	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	51878954725516736599453007649184128233002166515141802678344026843009130981794	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	13763840625179250035433979264965943775222987225009295272458687876544564979615	368	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	9525238558150840377767340605822406513721432664022336858694986674501184035534	367	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	61493606857590547221983218488007881701427136868122434475409195879437084651066	367	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	14685191784582404449435349746892076486593679973203885625752029855048408272882	328	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25774145484363770639705627058711272565151103494573942430562249853889820469851	326	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	69092049382377698725897126788822657921446452666412019723664951268709610561257	327	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				3 test runs
	chip_sw_all_escalation_resets	69608437853804888126659561154339804485902388170425825312769984648046918145214	317	UVM_ERROR @ 3563.544048 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3563.544048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_otp_ctrl_escalation	61918208450383466760637100924204262834537898079645154672094620374769199866145	316	UVM_ERROR @ 2987.489592 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2987.489592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	56914605401314137980633793446342743468672561648961022696747897500349305449281	312	UVM_ERROR @ 3516.688320 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3516.688320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	112781178895365277849507416785774446930573911053792184293792882894236512849763	369	UVM_INFO @ 9794.448516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	103248355025244486539827359147951954321143070037253015337706970455980204121698	369	UVM_INFO @ 11616.797675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	67888137088823329670789053449575937017831132122784117822049934141214382059270	341	UVM_INFO @ 5900.072529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26328410832523083338107620493389679125134186898596767128903161123629285637632	344	UVM_ERROR @ 13486.025000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 13486.025000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	61203731846086579738700680242870564301342220602692381470659068244117688649165	325	UVM_ERROR @ 7598.900000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7598.900000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	20219487004348043557965427112686059876173180200159735658211507811719038046310	395	UVM_ERROR @ 25373.488500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 25373.488500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	91531354338492352781642503074652709918616472263102576012839710740665479301529	310	UVM_INFO @ 12026.794717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	91237283215584690179412775686840065167890184580295896310479166028888003896391	310	UVM_INFO @ 12018.523023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	83505377839766048218495477517230180093385498706256706196837597703138891255332	334	UVM_INFO @ 20026.705627 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	90785171404256536400887495798513671771697177715515635369256161555371085808486	326	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	28606617757129115135960042215820707956325262503556165783480287552461403287486	325	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	42960895927776700598867173999973631986225395829759513402243331295502635165618	325	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				2 test runs
	chip_tl_errors	14941597658680313656726548702851062980730574451662514685609991040224732319311	217	TL item was: req: (cip_tl_seq_item@31524) { a_addr: 'h1069c a_data: 'h9955127d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h192f3 d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2679.103703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_csr_mem_rw_with_rand_reset	105704234885962124898469451250903042408482310979078044020441820497247060252841	242	TL item was: req: (cip_tl_seq_item@216536) { a_addr: 'h104e8 a_data: 'h548c077a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h18195 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 5830.447560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	4662962382231754884721932573851355358262080561632886777635959520552730290565	362	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	4549727220443833603380015216408161410329195584921876502018849972535768698364	325	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	32758549647080981625975259787623156987652274375584687218314999863268536470446	367	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	16986860119208957955378062962576327822055780138174437409801798150006561946804	326	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	20510300062617082286400280822763366205422399264148347696632795704560248177215	301	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	31097262941970352127318922197710801452354690964573141245877075245776917752319	451	UVM_INFO @ 3755.458000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	90979139831913702220139164122445033837806596721941328751832755215840646608782	327	UVM_INFO @ 3744.811574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	2368058168741608905078847931254228174351357448103358339737560678603914074976	309	UVM_INFO @ 2941.126246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	105639411759917898563943948699206935675767949367341819392671889566074459909841	342	UVM_INFO @ 8077.657538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	33873898323018501469535061420870048870219883072495261924774008284329249532027	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_transition	98164708691300596416475785039350226845826606646188073807419594456522111265076	305	UVM_INFO @ 26562.987185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	15499499064421869330790442909544965244447839657734390748322884067651126324108	316	UVM_ERROR @ 5918.391460 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 5918.391460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	79891564988876293972156885033379468264811488906993326186744575454321700700319	313	UVM_ERROR @ 3689.360676 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3689.360676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46134346887217566499309353186587728217820379688589862345089768903089743922989	332	UVM_INFO @ 34631.058874 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	79877325488524252232777886166922199914223290287494973732474231197377145168163	307	UVM_INFO @ 3128.393500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	75295379925045502434846544875258540356395702709628134760132013331797806586767	308	UVM_INFO @ 2561.722039 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	75348118707303187662126640652627528963300317620872409922469643893419752316490	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	73567804712416142403299297669260915902597905114085658165038791515535612289133	343	UVM_INFO @ 4007.761366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	26250115626877548510809652820897650792012314512155663220131247074044588521556	266	UVM_INFO @ 7504.198185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	91451511232360893983934302858232837261138721982307986318559334323142247234779	324	UVM_INFO @ 2697.324284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	39217514233494767458390910656135674410433664537575679833014649243978188760732	312	UVM_INFO @ 3395.511000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	47839358569884577500267601997681369085493958007294304532345185552449692761525	318	UVM_INFO @ 3370.430000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	2392889067092805188990697219746259066206298841185934867698878049980665948625	327	UVM_INFO @ 11728.871399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	114591472941113133598030509292506971581327402990899278251447740221520314600740	272	UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	72659352419101521491544803464300620145903682260050418675311632002919617723579	325	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	58550765120894473863338147467772952195717843836106933741433741215279076375373	328	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_no_meas	4133771085141580342693272327681304801284831446022115289468832575793318209139	319	UVM_INFO @ 16714.493275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	77951402791649141893196962422653533857855034931892694668303002993703167065204	327	UVM_ERROR @ 5242.505054 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 5242.505054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---