Simulation Results: clkmgr

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.58 %
  • code
  • 97.75 %
  • assert
  • 94.07 %
  • func
  • 85.93 %
  • line
  • 98.88 %
  • branch
  • 98.64 %
  • cond
  • 92.03 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.840s 19.566us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.950s 18.059us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.400s 313.985us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.300s 100.789us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.200s 273.198us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
clkmgr_csr_aliasing 1.300s 100.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.780s 32.340us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.150s 121.010us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.770s 31.992us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 15.631us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.840s 19.566us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.450s 1894.702us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.900s 2669.864us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.450s 1894.702us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 7.050s 1575.211us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.980s 15.922us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.430s 50.596us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.430s 50.596us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.950s 18.059us 1 1 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
clkmgr_csr_aliasing 1.300s 100.789us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 54.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.950s 18.059us 1 1 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
clkmgr_csr_aliasing 1.300s 100.789us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 54.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.640s 1.086us 0 1 0.00
clkmgr_tl_intg_err 1.790s 241.809us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 685.180s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 685.180s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 685.180s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 685.180s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.400s 346.096us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.790s 241.809us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.450s 1894.702us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.900s 2669.864us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 685.180s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.140s 148.406us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.830s 16.155us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.650s 15.843us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.030s 24.986us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.860s 16.043us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.640s 1.086us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.810s 26.974us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.640s 1.086us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.440s 1072.911us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 65.130s 19523.755us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 53162355044594541734253015526084864793264007914685483543183113882024532110559 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 72741746826941627367216901906250972833997439670617228952773242623866353037473 78
UVM_INFO @ 1085891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---