Simulation Results: edn/edn0

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 85.50 %
  • assert
  • 96.96 %
  • func
  • 79.56 %
  • line
  • 98.32 %
  • branch
  • 94.28 %
  • cond
  • 88.80 %
  • toggle
  • 91.26 %
  • FSM
  • 54.84 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 50.092us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.080s 14.633us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.910s 19.483us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.600s 316.990us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 55.851us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.070s 135.019us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.910s 19.483us 1 1 100.00
edn_csr_aliasing 1.150s 55.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.320s 49.395us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.320s 49.395us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.320s 49.395us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.020s 21.375us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 27.870us 1 1 100.00
errs 1 1 100.00
edn_err 1.040s 30.043us 1 1 100.00
disable 2 2 100.00
edn_disable 0.950s 42.075us 1 1 100.00
edn_disable_auto_req_mode 1.400s 38.633us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.340s 930.984us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 19.848us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 55.908us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.110s 666.227us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.110s 666.227us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.080s 14.633us 1 1 100.00
edn_csr_rw 0.910s 19.483us 1 1 100.00
edn_csr_aliasing 1.150s 55.851us 1 1 100.00
edn_same_csr_outstanding 1.030s 31.429us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.080s 14.633us 1 1 100.00
edn_csr_rw 0.910s 19.483us 1 1 100.00
edn_csr_aliasing 1.150s 55.851us 1 1 100.00
edn_same_csr_outstanding 1.030s 31.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.460s 950.260us 1 1 100.00
edn_tl_intg_err 1.790s 46.747us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 42.757us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 27.870us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.460s 950.260us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.460s 950.260us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.460s 950.260us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.460s 950.260us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 27.870us 1 1 100.00
edn_sec_cm 7.460s 950.260us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 27.870us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.790s 46.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.680s 2663.217us 1 1 100.00