Simulation Results: edn/edn1

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.38 %
  • code
  • 82.44 %
  • assert
  • 98.18 %
  • func
  • 81.51 %
  • line
  • 97.88 %
  • branch
  • 92.42 %
  • cond
  • 89.92 %
  • toggle
  • 87.68 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.800s 50.298us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.840s 25.359us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.860s 115.667us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.700s 223.619us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 334.505us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.370s 110.604us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.860s 115.667us 1 1 100.00
edn_csr_aliasing 1.150s 334.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.040s 132.548us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.040s 132.548us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.040s 132.548us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.780s 43.140us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 42.979us 1 1 100.00
errs 1 1 100.00
edn_err 0.780s 32.913us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 13.722us 1 1 100.00
edn_disable_auto_req_mode 1.270s 94.244us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.180s 273.328us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.750s 13.814us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 79.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.580s 186.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.580s 186.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.840s 25.359us 1 1 100.00
edn_csr_rw 0.860s 115.667us 1 1 100.00
edn_csr_aliasing 1.150s 334.505us 1 1 100.00
edn_same_csr_outstanding 0.960s 62.238us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.840s 25.359us 1 1 100.00
edn_csr_rw 0.860s 115.667us 1 1 100.00
edn_csr_aliasing 1.150s 334.505us 1 1 100.00
edn_same_csr_outstanding 0.960s 62.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.470s 450.054us 1 1 100.00
edn_tl_intg_err 1.580s 173.252us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 22.130us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 42.979us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.470s 450.054us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.470s 450.054us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.470s 450.054us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.470s 450.054us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 42.979us 1 1 100.00
edn_sec_cm 2.470s 450.054us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 42.979us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.580s 173.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.320s 11089.240us 1 1 100.00