Simulation Results: flash_ctrl

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 94.11 %
  • assert
  • 96.77 %
  • func
  • 96.04 %
  • line
  • 95.96 %
  • branch
  • 97.08 %
  • cond
  • 93.97 %
  • toggle
  • 97.81 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 102.540s 69.080us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 17.060s 56.392us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.730s 36.647us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 56.350s 8126.602us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.570s 862.910us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.450s 70.428us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
flash_ctrl_csr_aliasing 22.570s 862.910us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.340s 56.651us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.260s 19.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.560s 29.874us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 40.710s 95.966us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1206.060s 142869.605us 1 1 100.00
flash_ctrl_hw_rma_reset 561.650s 80153.300us 1 1 100.00
flash_ctrl_lcmgr_intg 7.240s 63.499us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1256.460s 775823.714us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 214.390s 13990.444us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.580s 77.826us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2469.060s 138712.764us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 55.390s 3038.979us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.590s 231.002us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.270s 41.810us 1 1 100.00
flash_ctrl_re_evict 19.590s 234.932us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 32.420s 26.341us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 32.420s 26.341us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 112.250s 12743.011us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.590s 1039.686us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 37.630s 32.937us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 363.660s 25226.288us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 441.210s 512.104us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 935.460s 507.179us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.480s 65.489us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 117.450s 1470.870us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.980s 24.451us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.460s 74.760us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 112.530s 942.723us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 119.730s 5390.419us 1 1 100.00
flash_ctrl_otp_reset 43.710s 153.461us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1206.060s 142869.605us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 182.350s 4889.105us 1 1 100.00
flash_ctrl_intr_wr 63.670s 3385.264us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 181.470s 13029.570us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 198.980s 134166.928us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 43.070s 7629.318us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.100s 682.673us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.980s 103.640us 1 1 100.00
flash_ctrl_ro_derr 99.940s 1325.254us 1 1 100.00
flash_ctrl_rw_derr 161.370s 2055.659us 1 1 100.00
flash_ctrl_derr_detect 105.510s 3052.387us 1 1 100.00
flash_ctrl_integrity 342.790s 16823.470us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.740s 107.634us 1 1 100.00
flash_ctrl_ro_serr 96.400s 9739.394us 1 1 100.00
flash_ctrl_rw_serr 101.590s 1565.905us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 50.610s 1761.206us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 54.050s 1744.477us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 123.120s 12027.421us 1 1 100.00
flash_ctrl_write_word_sweep 7.760s 156.471us 1 1 100.00
flash_ctrl_read_word_sweep 9.010s 31.407us 1 1 100.00
flash_ctrl_ro 85.810s 1449.553us 1 1 100.00
flash_ctrl_rw 361.050s 3874.909us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.510s 1796.858us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 568.620s 41396.212us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 53.190s 10037.265us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.300s 177.428us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.540s 18.919us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.930s 177.198us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.930s 177.198us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.730s 36.647us 1 1 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
flash_ctrl_csr_aliasing 22.570s 862.910us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.690s 399.006us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.730s 36.647us 1 1 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
flash_ctrl_csr_aliasing 22.570s 862.910us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.690s 399.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 34.110s 1657.843us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
flash_ctrl_tl_intg_err 313.590s 1627.220us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 313.590s 1627.220us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 313.590s 1627.220us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.140s 140.042us 1 1 100.00
flash_ctrl_wr_intg 6.900s 50.758us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 102.540s 69.080us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 43.710s 153.461us 1 1 100.00
flash_ctrl_disable 9.980s 24.451us 1 1 100.00
flash_ctrl_sec_info_access 49.630s 5478.293us 1 1 100.00
flash_ctrl_connect 7.460s 74.760us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.030s 40.136us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.390s 63.878us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 15.540s 22.189us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.980s 24.451us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.140s 140.042us 1 1 100.00
flash_ctrl_access_after_disable 6.270s 42.735us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.440s 69.804us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.980s 24.451us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.590s 1039.686us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 361.050s 3874.909us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 101.590s 1565.905us 1 1 100.00
flash_ctrl_rw_derr 161.370s 2055.659us 1 1 100.00
flash_ctrl_integrity 342.790s 16823.470us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1206.060s 142869.605us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.990s 781.500us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.160s 21.484us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 11.720s 111.303us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1754.940s 6102.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.550s 242.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 39.860s 118.595us 1 1 100.00