Simulation Results: hmac

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.53 %
  • code
  • 97.62 %
  • assert
  • 97.16 %
  • func
  • 43.80 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.850s 529.679us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 107.646us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.740s 33.478us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.510s 2028.927us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.200s 917.787us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.220s 29.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.740s 33.478us 1 1 100.00
hmac_csr_aliasing 2.200s 917.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 71.020s 37348.690us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 47.090s 1590.731us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 230.120s 40954.032us 1 1 100.00
hmac_test_sha384_vectors 20.500s 619.529us 1 1 100.00
hmac_test_sha512_vectors 372.850s 59256.646us 1 1 100.00
hmac_test_hmac256_vectors 10.910s 443.009us 1 1 100.00
hmac_test_hmac384_vectors 9.140s 4280.227us 1 1 100.00
hmac_test_hmac512_vectors 9.160s 331.592us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 28.610s 3765.882us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 657.080s 14674.133us 1 1 100.00
error 1 1 100.00
hmac_error 0.770s 63.805us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 90.640s 23652.241us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.850s 529.679us 1 1 100.00
hmac_long_msg 71.020s 37348.690us 1 1 100.00
hmac_back_pressure 47.090s 1590.731us 1 1 100.00
hmac_datapath_stress 657.080s 14674.133us 1 1 100.00
hmac_burst_wr 28.610s 3765.882us 1 1 100.00
hmac_stress_all 1225.080s 149417.088us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.850s 529.679us 1 1 100.00
hmac_long_msg 71.020s 37348.690us 1 1 100.00
hmac_back_pressure 47.090s 1590.731us 1 1 100.00
hmac_datapath_stress 657.080s 14674.133us 1 1 100.00
hmac_wipe_secret 90.640s 23652.241us 1 1 100.00
hmac_test_sha256_vectors 230.120s 40954.032us 1 1 100.00
hmac_test_sha384_vectors 20.500s 619.529us 1 1 100.00
hmac_test_sha512_vectors 372.850s 59256.646us 1 1 100.00
hmac_test_hmac256_vectors 10.910s 443.009us 1 1 100.00
hmac_test_hmac384_vectors 9.140s 4280.227us 1 1 100.00
hmac_test_hmac512_vectors 9.160s 331.592us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.850s 529.679us 1 1 100.00
hmac_long_msg 71.020s 37348.690us 1 1 100.00
hmac_back_pressure 47.090s 1590.731us 1 1 100.00
hmac_datapath_stress 657.080s 14674.133us 1 1 100.00
hmac_burst_wr 28.610s 3765.882us 1 1 100.00
hmac_error 0.770s 63.805us 1 1 100.00
hmac_wipe_secret 90.640s 23652.241us 1 1 100.00
hmac_test_sha256_vectors 230.120s 40954.032us 1 1 100.00
hmac_test_sha384_vectors 20.500s 619.529us 1 1 100.00
hmac_test_sha512_vectors 372.850s 59256.646us 1 1 100.00
hmac_test_hmac256_vectors 10.910s 443.009us 1 1 100.00
hmac_test_hmac384_vectors 9.140s 4280.227us 1 1 100.00
hmac_test_hmac512_vectors 9.160s 331.592us 1 1 100.00
hmac_stress_all 1225.080s 149417.088us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1225.080s 149417.088us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 44.448us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 22.032us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.500s 867.995us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.500s 867.995us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 107.646us 1 1 100.00
hmac_csr_rw 0.740s 33.478us 1 1 100.00
hmac_csr_aliasing 2.200s 917.787us 1 1 100.00
hmac_same_csr_outstanding 1.970s 295.013us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 107.646us 1 1 100.00
hmac_csr_rw 0.740s 33.478us 1 1 100.00
hmac_csr_aliasing 2.200s 917.787us 1 1 100.00
hmac_same_csr_outstanding 1.970s 295.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.820s 403.972us 1 1 100.00
hmac_tl_intg_err 3.400s 242.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.400s 242.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.850s 529.679us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.420s 295.628us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 87.560s 12659.186us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.020s 15.158us 1 1 100.00