Simulation Results: i2c

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.12 %
  • code
  • 81.10 %
  • assert
  • 97.25 %
  • func
  • 80.02 %
  • line
  • 96.35 %
  • branch
  • 92.12 %
  • cond
  • 84.52 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
82.93%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 34.170s 2649.365us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 5.980s 3153.957us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.960s 20.385us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.710s 50.508us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.540s 1369.572us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.340s 68.037us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.210s 49.581us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.710s 50.508us 1 1 100.00
i2c_csr_aliasing 1.340s 68.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.780s 56.146us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 8.490s 684.882us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 306.370s 47266.003us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.670s 18.570us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 60.940s 16563.032us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 23.200s 2916.166us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.460s 570.327us 1 1 100.00
i2c_host_fifo_fmt_empty 8.710s 352.287us 1 1 100.00
i2c_host_fifo_reset_rx 4.150s 278.345us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 53.310s 13133.384us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 6.230s 599.168us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.110s 87.450us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.370s 543.043us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 217.620s 32791.054us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.930s 3291.227us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 10.880s 1397.384us 1 1 100.00
i2c_target_intr_smoke 5.040s 1554.670us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.220s 328.772us 1 1 100.00
i2c_target_fifo_reset_tx 1.220s 401.747us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 216.470s 50097.279us 1 1 100.00
i2c_target_stress_rd 10.880s 1397.384us 1 1 100.00
i2c_target_intr_stress_wr 40.120s 12687.486us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.190s 4929.801us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 55.910s 2385.989us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.840s 771.593us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 5.610s 10056.378us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.210s 2497.018us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.350s 512.636us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 306.370s 47266.003us 1 1 100.00
i2c_host_perf_precise 2.240s 173.282us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 6.230s 599.168us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 0.770s 13.438us 0 1 0.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.030s 570.826us 1 1 100.00
i2c_target_nack_acqfull_addr 1.570s 509.854us 1 1 100.00
i2c_target_nack_txstretch 1.170s 189.541us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 5.590s 2340.297us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.580s 1721.082us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.830s 23.397us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.800s 15.238us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.560s 152.406us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.560s 152.406us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.960s 20.385us 1 1 100.00
i2c_csr_rw 0.710s 50.508us 1 1 100.00
i2c_csr_aliasing 1.340s 68.037us 1 1 100.00
i2c_same_csr_outstanding 0.970s 53.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.960s 20.385us 1 1 100.00
i2c_csr_rw 0.710s 50.508us 1 1 100.00
i2c_csr_aliasing 1.340s 68.037us 1 1 100.00
i2c_same_csr_outstanding 0.970s 53.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.790s 75.688us 1 1 100.00
i2c_sec_cm 1.130s 426.613us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.790s 75.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 11.560s 3997.519us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.120s 251.683us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.560s 1051.195us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 98410560573423760998088537768627210928040391022813799767459217363154124818450 80
UVM_INFO @ 56145664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 36134102600891855562497473161441269611646086778722569588824290168978340599994 91
UVM_INFO @ 684881521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 16991899530376979400367159787490359661252569907340899663249804619054908716343 97
UVM_INFO @ 1051195411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 36751776529851558338510308147465299592654610522111895931740083205631481670588 84
UVM_INFO @ 543043133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 54834416771932708359796263301438296483468706700266750039644192511005090164480 78
UVM_INFO @ 251683349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 83195114680962108061071747564060310906636655046072446314149670338656257598585 79
UVM_INFO @ 10056377665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 89468755269386186093859350710490647977650863276805751675980493155425551297908 92
UVM_INFO @ 3997519459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_mode_toggle 14700661010548799409277509060045003281124775239587727213979624010380915372685 87
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
Error-[CNST-CIF] Constraints inconsistency failure 1 test run
i2c_target_tx_stretch_ctrl 128508723960473916989611936872437607165566954475483899117814972361045983956 124
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 33698342950863355951921130386954843812860723782025175739114947390469651069375 78
UVM_INFO @ 189541308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---