Simulation Results: kmac/masked

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.47 %
  • code
  • 69.71 %
  • assert
  • 97.75 %
  • func
  • 79.94 %
  • line
  • 96.24 %
  • branch
  • 90.65 %
  • cond
  • 86.24 %
  • toggle
  • 29.23 %
  • FSM
  • 46.20 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 58.760s 11537.727us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.930s 62.158us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.270s 31.110us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 22.790s 25827.600us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.590s 1547.134us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.380s 131.114us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.270s 31.110us 1 1 100.00
kmac_csr_aliasing 7.590s 1547.134us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.920s 22.477us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.100s 97.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 367.040s 11421.225us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 262.740s 22549.666us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2543.870s 101837.374us 1 1 100.00
kmac_test_vectors_sha3_256 27.100s 5977.953us 1 1 100.00
kmac_test_vectors_sha3_384 1553.840s 164445.700us 1 1 100.00
kmac_test_vectors_sha3_512 1160.650s 360818.043us 1 1 100.00
kmac_test_vectors_shake_128 118.550s 16974.913us 1 1 100.00
kmac_test_vectors_shake_256 117.260s 10406.562us 1 1 100.00
kmac_test_vectors_kmac 2.120s 308.202us 1 1 100.00
kmac_test_vectors_kmac_xof 1.980s 37.525us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 102.580s 8516.424us 1 1 100.00
app 0 1 0.00
kmac_app 3.990s 215.023us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 3.650s 80.164us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 5.960s 1294.587us 0 1 0.00
error 0 1 0.00
kmac_error 18.260s 636.433us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.060s 102.987us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.120s 23.473us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 13.750s 1824.863us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.300s 298.215us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.790s 94.165us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.360s 46.064us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 247.090s 10653.496us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.810s 40.566us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.040s 72.597us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.720s 106.542us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.720s 106.542us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.930s 62.158us 1 1 100.00
kmac_csr_rw 1.270s 31.110us 1 1 100.00
kmac_csr_aliasing 7.590s 1547.134us 1 1 100.00
kmac_same_csr_outstanding 2.690s 1842.511us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.930s 62.158us 1 1 100.00
kmac_csr_rw 1.270s 31.110us 1 1 100.00
kmac_csr_aliasing 7.590s 1547.134us 1 1 100.00
kmac_same_csr_outstanding 2.690s 1842.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.830s 115.271us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.830s 115.271us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.830s 115.271us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.830s 115.271us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.290s 482.454us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 43.140s 9270.945us 1 1 100.00
kmac_tl_intg_err 4.030s 458.518us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.030s 458.518us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.360s 46.064us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 58.760s 11537.727us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 102.580s 8516.424us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.830s 115.271us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 43.140s 9270.945us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 43.140s 9270.945us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 43.140s 9270.945us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 58.760s 11537.727us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.360s 46.064us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 43.140s 9270.945us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 5.320s 266.377us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 58.760s 11537.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 8.060s 358.232us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 7 test runs
kmac_sideload_invalid 105649739105682043272664905607891146848773246657245028116947700156796376510625 76
UVM_INFO @ 23473123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 66439799133352486872532648482610813523414362764193965151116876022419285504283 78
UVM_INFO @ 215022639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 26131019077249711525365697619521384471060480851910010867593288843529926721802 78
UVM_INFO @ 80164165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 36982361040745830543386152017264789939442977424696356285874252002637716991172 79
UVM_INFO @ 1294586961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 80432820702623153316852388745366782128046371670424161178268448954766472882892 86
UVM_INFO @ 636432626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 21588002394047745393810757776340663460197170540284529792614191738831641527958 218
UVM_INFO @ 10653495968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 101043553454217662647654823710865119743861362588902314804480008749978428657577 99
UVM_INFO @ 358231761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_key_error 46419342122211251072033820120886480627245809469239470590467024861180247761857 78
UVM_ERROR @ 102987498 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 102987498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 18506475135226789909377920735371154050855046731976181569226692622444090016002 78
UVM_ERROR @ 94164905 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 94164905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 112463489128009512542502429885871837487807968058670540114919629185561400996396 80
UVM_INFO @ 266377066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---