Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.40 %
  • code
  • 83.16 %
  • assert
  • 94.97 %
  • func
  • 93.06 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.15 %
  • toggle
  • 84.09 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.230s 63.138us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.180s 14.739us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 22.441us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.960s 195.247us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 20.903us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 32.689us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 22.441us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 20.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.970s 120.763us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.060s 217.374us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.020s 14.275us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.740s 81.089us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.730s 300.155us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_prog_failure 1.740s 81.089us 1 1 100.00
lc_ctrl_errors 4.730s 300.155us 1 1 100.00
lc_ctrl_security_escalation 6.440s 7161.565us 1 1 100.00
lc_ctrl_jtag_state_failure 20.400s 8980.062us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.190s 210.440us 1 1 100.00
lc_ctrl_jtag_errors 44.050s 2811.256us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.140s 546.922us 1 1 100.00
lc_ctrl_jtag_state_post_trans 20.770s 1024.692us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.190s 210.440us 1 1 100.00
lc_ctrl_jtag_errors 44.050s 2811.256us 1 1 100.00
lc_ctrl_jtag_access 2.420s 811.059us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.800s 1008.928us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.040s 58.610us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.510s 122.094us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 22.050s 5332.691us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.500s 915.080us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.210s 176.736us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 1334.447us 1 1 100.00
lc_ctrl_jtag_alert_test 1.670s 71.320us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 26.190s 1582.669us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 45.120us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 27.470s 1588.973us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.950s 27.622us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 28.706us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 28.706us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.180s 14.739us 1 1 100.00
lc_ctrl_csr_rw 0.860s 22.441us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 20.903us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.160s 60.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.180s 14.739us 1 1 100.00
lc_ctrl_csr_rw 0.860s 22.441us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 20.903us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.160s 60.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
lc_ctrl_tl_intg_err 3.040s 1605.193us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.040s 1605.193us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.060s 217.374us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.770s 295.013us 1 1 100.00
lc_ctrl_sec_cm 7.280s 232.347us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.440s 7161.565us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.970s 120.763us 1 1 100.00
lc_ctrl_jtag_state_post_trans 20.770s 1024.692us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.040s 1600.570us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.040s 1600.570us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.680s 10512.073us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.320s 248.541us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.320s 248.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.140s 3146.458us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 40763671968211553418754311173066752211017012040796530089803312702430038893609 1801
UVM_INFO @ 1588973498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---