Simulation Results: otbn

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.27 %
  • code
  • 95.45 %
  • assert
  • 90.35 %
  • func
  • 97.03 %
  • block
  • 99.40 %
  • line
  • 99.54 %
  • branch
  • 92.62 %
  • toggle
  • 92.06 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 69.935us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 26.000s 24.421us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 22.000s 84.504us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 28.000s 47.877us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 24.000s 81.444us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 24.000s 40.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 22.000s 84.504us 1 1 100.00
otbn_csr_aliasing 24.000s 81.444us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 36.000s 769.053us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 330.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 18.000s 306.050us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 55.000s 161.760us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 94.000s 2153.299us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 56.000s 193.480us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 27.000s 90.355us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 31.430us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 11.000s 42.388us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 28.000s 35.455us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 18.000s 18.539us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 33.898us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 33.898us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 26.000s 24.421us 1 1 100.00
otbn_csr_rw 22.000s 84.504us 1 1 100.00
otbn_csr_aliasing 24.000s 81.444us 1 1 100.00
otbn_same_csr_outstanding 5.000s 39.794us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 26.000s 24.421us 1 1 100.00
otbn_csr_rw 22.000s 84.504us 1 1 100.00
otbn_csr_aliasing 24.000s 81.444us 1 1 100.00
otbn_same_csr_outstanding 5.000s 39.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 23.000s 18.362us 1 1 100.00
otbn_dmem_err 25.000s 50.790us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 28.000s 61.598us 1 1 100.00
otbn_controller_ispr_rdata_err 27.000s 63.138us 0 1 0.00
otbn_mac_bignum_acc_err 13.000s 411.678us 1 1 100.00
otbn_urnd_err 5.000s 31.814us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 20.000s 22.055us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 71.612us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 22.383us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
otbn_tl_intg_err 16.000s 434.382us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 8.000s 18.792us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 69.935us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 25.000s 50.790us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 23.000s 18.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 434.382us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 27.000s 90.355us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 23.000s 18.362us 1 1 100.00
otbn_dmem_err 25.000s 50.790us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 31.430us 1 1 100.00
otbn_illegal_mem_acc 20.000s 22.055us 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 23.000s 18.362us 1 1 100.00
otbn_dmem_err 25.000s 50.790us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 31.430us 1 1 100.00
otbn_illegal_mem_acc 20.000s 22.055us 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 27.000s 90.355us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 23.000s 18.362us 1 1 100.00
otbn_dmem_err 25.000s 50.790us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 31.430us 1 1 100.00
otbn_illegal_mem_acc 20.000s 22.055us 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 24.000s 28.649us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 20.592us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 29.000s 355.787us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 29.000s 355.787us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 96.341us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 64.691us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 27.448us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 27.448us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 10.617us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 94.000s 2153.299us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 50.272us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 36.891us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 243.000s 1411.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 9.000s 25.892us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 28.696us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_controller_ispr_rdata_err 95950951786948806237254281854708227145585645100122620306753748935754259516504 110
UVM_INFO @ 63138160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 84467031875392883254359602677843790872952167266449938720941508201228856944177 156
UVM_INFO @ 25891946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 21401338443075107313250515660726141806771560658291940016756721063341902947970 91
UVM_INFO @ 18791517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---