Simulation Results: otp_ctrl

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.89 %
  • code
  • 78.84 %
  • assert
  • 94.05 %
  • func
  • 72.77 %
  • line
  • 88.55 %
  • branch
  • 83.36 %
  • cond
  • 89.88 %
  • toggle
  • 87.45 %
  • FSM
  • 44.97 %
Validation stages
V1
88.89%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.550s 827.760us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.880s 106.843us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.510s 95.322us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.110s 4938.933us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.060s 188.189us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.350s 35.214us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.510s 95.322us 1 1 100.00
otp_ctrl_csr_aliasing 3.060s 188.189us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.210s 137.821us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.150s 38.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.680s 2047.331us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.420s 298.743us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 19.610s 2116.038us 1 1 100.00
otp_ctrl_check_fail 4.450s 973.462us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.460s 413.575us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.430s 434.865us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.720s 2061.867us 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 10.040s 402.258us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 9.560s 1051.619us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 27.110s 17776.079us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 104.250s 25622.654us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.220s 42.339us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.540s 194.516us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.880s 237.753us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.880s 237.753us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.880s 106.843us 1 1 100.00
otp_ctrl_csr_rw 1.510s 95.322us 1 1 100.00
otp_ctrl_csr_aliasing 3.060s 188.189us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.050s 192.118us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.880s 106.843us 1 1 100.00
otp_ctrl_csr_rw 1.510s 95.322us 1 1 100.00
otp_ctrl_csr_aliasing 3.060s 188.189us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.050s 192.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
otp_ctrl_tl_intg_err 14.750s 2553.774us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.750s 2553.774us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_ctrl_macro_errs 9.560s 1051.619us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_ctrl_macro_errs 9.560s 1051.619us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.830s 386.148us 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.420s 298.743us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.450s 973.462us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.240s 2721.600us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 133.270s 44614.895us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.460s 413.575us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.310s 5770.830us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 9.560s 1051.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.050s 8079.073us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 27.700s 2941.767us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 2 test runs
otp_ctrl_stress_all_with_rand_reset 37363096582788230687695359643983802672869302239039452649913700700380607124878 21808
UVM_INFO @ 2941766810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 86093662574622746884071592090614010826841805130188049901710763677143497053014 92
UVM_INFO @ 35214458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---