Simulation Results: pattgen

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 25.039us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 65.959us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 79.912us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 670.261us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 96.852us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 187.494us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 79.912us 1 1 100.00
pattgen_csr_aliasing 2.000s 96.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 3602.054s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 22.000s 5355.999us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 62.786us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 6675.000s 1624574.324us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 17.123us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 27.126us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 368.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 368.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 65.959us 1 1 100.00
pattgen_csr_rw 1.000s 79.912us 1 1 100.00
pattgen_csr_aliasing 2.000s 96.852us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 16.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 65.959us 1 1 100.00
pattgen_csr_rw 1.000s 79.912us 1 1 100.00
pattgen_csr_aliasing 2.000s 96.852us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 16.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 96.726us 1 1 100.00
pattgen_sec_cm 1.000s 143.983us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 96.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 21.000s 4123.529us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 3.000s 253.413us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
pattgen_perf 68771474162415512472852823527734261506046013956568111620340866354034958771136 None
UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 47523814839987779391779274862490072112490272592614796946059818559579043344749 143
UVM_ERROR @ 918995350 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 918995350 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 919082308 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]