Simulation Results: pwrmgr

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.71 %
  • code
  • 92.90 %
  • assert
  • 96.87 %
  • func
  • 97.36 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.62 %
  • toggle
  • 99.62 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 40.386us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.800s 31.916us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.730s 41.108us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.370s 62.099us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.870s 57.263us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.980s 65.181us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.730s 41.108us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 57.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.800s 364.001us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.800s 364.001us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.900s 161.773us 1 1 100.00
pwrmgr_lowpower_invalid 0.620s 49.865us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.940s 96.716us 1 1 100.00
pwrmgr_reset_invalid 0.700s 34.658us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.940s 96.716us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.990s 239.954us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.680s 69.973us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.630s 60.371us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.650s 35.421us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 54.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.980s 52.491us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.980s 52.491us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.800s 31.916us 1 1 100.00
pwrmgr_csr_rw 0.730s 41.108us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 57.263us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 89.292us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.800s 31.916us 1 1 100.00
pwrmgr_csr_rw 0.730s 41.108us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 57.263us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 89.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.940s 255.219us 1 1 100.00
pwrmgr_sec_cm 1.590s 664.455us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.590s 664.455us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.590s 664.455us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.940s 255.219us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.420s 990.246us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.990s 239.954us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.640s 865.004us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.900s 75.664us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.610s 38.857us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.590s 664.455us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.590s 664.455us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.590s 664.455us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.640s 70.079us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.590s 49.032us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.900s 343.330us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 41.108us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 41.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.760s 355.061us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 3.570s 2878.187us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 61389549130109563278442139775291455677119500177885959674376823804398895274579 79
UVM_ERROR @ 355060811 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 355060811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown 1 test run
pwrmgr_reset_invalid 34844738993309412432096698307491889567796031865488482776654069053596615235523 81
UVM_INFO @ 34657990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---