Simulation Results: rom_ctrl/64kb

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.64 %
  • code
  • 95.78 %
  • assert
  • 97.24 %
  • func
  • 96.90 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 95.54 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.150s 1388.674us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.620s 1146.086us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.860s 370.326us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.350s 205.370us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 532.061us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.310s 1103.847us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.860s 370.326us 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 532.061us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.540s 514.285us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.540s 1024.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.220s 1906.123us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 30.320s 1074.636us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.170s 1879.032us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.890s 1069.614us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.300s 370.597us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.300s 370.597us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.620s 1146.086us 1 1 100.00
rom_ctrl_csr_rw 5.860s 370.326us 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 532.061us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.380s 1585.230us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.620s 1146.086us 1 1 100.00
rom_ctrl_csr_rw 5.860s 370.326us 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 532.061us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.380s 1585.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.050s 2779.836us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 241.730s 1575.219us 1 1 100.00
rom_ctrl_tl_intg_err 102.020s 1329.879us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 241.730s 1575.219us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 241.730s 1575.219us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 241.730s 1575.219us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 241.730s 1575.219us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.150s 1388.674us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.150s 1388.674us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.150s 1388.674us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 102.020s 1329.879us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
rom_ctrl_kmac_err_chk 14.170s 1879.032us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 25364.949us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.050s 2779.836us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 241.730s 1575.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 38.400s 9554.454us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 66357210832440682555770124057022612180373702968152546616546438572396726126311 79
UVM_INFO @ 1906122572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---