Simulation Results: rstmgr

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.16 %
  • code
  • 99.31 %
  • assert
  • 98.39 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.110s 136.065us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.820s 129.356us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.820s 69.607us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.710s 2473.292us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.940s 230.489us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.300s 201.027us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.820s 69.607us 1 1 100.00
rstmgr_csr_aliasing 1.940s 230.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.870s 103.403us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.150s 524.903us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.420s 285.156us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.520s 985.910us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.520s 985.910us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.520s 985.910us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.520s 985.910us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 9.710s 3947.518us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 93.619us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.790s 606.124us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.790s 606.124us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 129.356us 1 1 100.00
rstmgr_csr_rw 0.820s 69.607us 1 1 100.00
rstmgr_csr_aliasing 1.940s 230.489us 1 1 100.00
rstmgr_same_csr_outstanding 0.910s 91.313us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 129.356us 1 1 100.00
rstmgr_csr_rw 0.820s 69.607us 1 1 100.00
rstmgr_csr_aliasing 1.940s 230.489us 1 1 100.00
rstmgr_same_csr_outstanding 0.910s 91.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.340s 9925.267us 1 1 100.00
rstmgr_tl_intg_err 2.460s 798.028us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.340s 9925.267us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.340s 9925.267us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.460s 798.028us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.050s 192.954us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.490s 1408.783us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.580s 302.198us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.340s 9925.267us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 69.607us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 69.607us 1 1 100.00