Simulation Results: rv_timer

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.40 %
  • code
  • 100.00 %
  • assert
  • 98.09 %
  • func
  • 79.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.670s 81.192us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 252.328us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.660s 28.182us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.950s 172.439us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.720s 92.369us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.280s 33.158us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.660s 28.182us 1 1 100.00
rv_timer_csr_aliasing 0.720s 92.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.620s 177.312us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.390s 4119.381us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.760s 84.178us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.760s 84.178us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.410s 3837.961us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 27.477us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.580s 18.178us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.370s 206.161us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.370s 206.161us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 252.328us 1 1 100.00
rv_timer_csr_rw 0.660s 28.182us 1 1 100.00
rv_timer_csr_aliasing 0.720s 92.369us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 32.979us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 252.328us 1 1 100.00
rv_timer_csr_rw 0.660s 28.182us 1 1 100.00
rv_timer_csr_aliasing 0.720s 92.369us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 32.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.900s 44.059us 1 1 100.00
rv_timer_tl_intg_err 0.930s 59.711us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.930s 59.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.730s 76.177us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.620s 44.157us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 17.900s 12510.912us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 114171994414674097298139326680702827740598603527530256264522634541742934804719 77
UVM_INFO @ 76176778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 36693555438268267614375064561150153948141234306692871615909412595993381402923 75
UVM_INFO @ 177311676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 80915292672105232912357386343245511696109774059225562327925511635459868302153 75
UVM_INFO @ 44156857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---