Simulation Results: sram_ctrl/main

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.37 %
  • code
  • 96.77 %
  • assert
  • 97.55 %
  • func
  • 94.80 %
  • block
  • 96.10 %
  • line
  • 96.83 %
  • branch
  • 94.17 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 732.568us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 34.150us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.037us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 824.681us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.940us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1314.185us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 43.037us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.940us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 183.000s 22718.509us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 97.000s 17188.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 12.000s 10564.956us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 144.000s 5356.571us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 151.000s 69969.909us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 49.000s 22842.652us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2388.784us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 25.000s 26416.456us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 14021.840us 1 1 100.00
sram_ctrl_partial_access_b2b 245.000s 40411.360us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 6.000s 2870.104us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 2641.578us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2674.106us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 14.000s 1540.712us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 741.796us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 131.000s 10196.245us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 63.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 70.298us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 70.298us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 34.150us 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.037us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.940us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.086us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 34.150us 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.037us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.940us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 15416.614us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 3917.779us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 805.934us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 3917.779us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 805.934us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 1540.712us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 1540.712us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.037us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 25.000s 26416.456us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 26416.456us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 26416.456us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2388.784us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 680.942us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 15416.614us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 1213.448us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 732.568us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 732.568us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 25.000s 26416.456us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 3917.779us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2388.784us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 3917.779us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 3917.779us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 732.568us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 3917.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 18.000s 4240.069us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 14935078784226349698417156189494149898960045535592656519237459716714298424629 86
UVM_INFO @ 2870104263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 89344395680014146812459833545919594749153456345819170581374286636088012639489 86
UVM_INFO @ 2641577921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 94203528894617980513000426000672742486716191425558270959934360429472270410359 86
UVM_INFO @ 2674106097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---