Simulation Results: sram_ctrl/ret

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.93 %
  • code
  • 82.52 %
  • assert
  • 97.26 %
  • func
  • 93.00 %
  • block
  • 92.68 %
  • line
  • 93.64 %
  • branch
  • 87.48 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 134.671us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 33.065us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 38.905us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 204.146us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 57.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 141.629us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 38.905us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 57.315us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 206.558us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 631.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 4214.404us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 156.000s 13620.204us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 622.767us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 4533.594us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 638.418us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 535.264us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 146.555us 1 1 100.00
sram_ctrl_partial_access_b2b 126.000s 3764.893us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 72.586us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 146.183us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 64.829us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 678.149us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 30.133us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 34.000s 13044.219us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 49.355us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 23.149us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 23.149us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 33.065us 1 1 100.00
sram_ctrl_csr_rw 1.000s 38.905us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 57.315us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 62.631us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 33.065us 1 1 100.00
sram_ctrl_csr_rw 1.000s 38.905us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 57.315us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 62.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1535.667us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1231.601us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1054.512us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1231.601us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1054.512us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 678.149us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 678.149us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 38.905us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 535.264us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 535.264us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 535.264us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 638.418us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 39.812us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1535.667us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 34.426us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 134.671us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 134.671us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 535.264us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1231.601us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 638.418us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1231.601us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1231.601us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 134.671us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1231.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 2213.397us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 21633604913320026633632951449373483777718102405114973546087817124420842229274 86
UVM_INFO @ 72586335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 109800839867980061406843181501785326238956328295686434077167444692927320260027 86
UVM_INFO @ 146183473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 427573407125474553488138767379089464132339169038994279007008438662141405324 86
UVM_INFO @ 64828530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---