Simulation Results: sysrst_ctrl

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.56 %
  • code
  • 92.64 %
  • assert
  • 92.53 %
  • func
  • 62.52 %
  • line
  • 97.08 %
  • branch
  • 97.22 %
  • cond
  • 94.56 %
  • toggle
  • 100.00 %
  • FSM
  • 74.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.030s 2193.510us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.220s 2448.851us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.190s 2202.188us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.460s 2315.432us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.250s 6031.324us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.320s 2041.778us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 35.230s 39138.511us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 2981.090us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.700s 2116.134us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.320s 2041.778us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 2981.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 42.730s 96750.855us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 35.810s 104332.379us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.120s 3164.820us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.480s 5266.369us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.180s 2576.828us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.510s 2251.862us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.120s 3728.259us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.810s 2619.956us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.130s 4958.627us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 9.110s 34489.716us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 9.950s 67352.985us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.660s 2030.941us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.590s 2054.045us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.810s 2161.708us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.810s 2161.708us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.250s 6031.324us 1 1 100.00
sysrst_ctrl_csr_rw 4.320s 2041.778us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 2981.090us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 1.780s 5189.585us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.250s 6031.324us 1 1 100.00
sysrst_ctrl_csr_rw 4.320s 2041.778us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 2981.090us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 1.780s 5189.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 17.070s 42160.648us 1 1 100.00
sysrst_ctrl_tl_intg_err 40.320s 42602.438us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 40.320s 42602.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 10.550s 5884.928us 1 1 100.00