Simulation Results: uart

 
17/06/2026 15:30:26 DVSim: v1.49.9 sha: 8899f65 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.47 %
  • code
  • 96.80 %
  • assert
  • 97.12 %
  • func
  • 59.50 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.02 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.290s 277.430us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.880s 31.918us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.690s 12.878us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.790s 152.453us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.710s 52.683us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.020s 24.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.690s 12.878us 1 1 100.00
uart_csr_aliasing 0.710s 52.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 45.510s 114275.941us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.290s 277.430us 1 1 100.00
uart_tx_rx 45.510s 114275.941us 1 1 100.00
parity_error 2 2 100.00
uart_intr 20.010s 53074.452us 1 1 100.00
uart_rx_parity_err 48.580s 117380.881us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 45.510s 114275.941us 1 1 100.00
uart_intr 20.010s 53074.452us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 27.890s 77772.303us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 26.500s 122296.169us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 7.520s 32201.136us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 20.010s 53074.452us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 20.010s 53074.452us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 20.010s 53074.452us 1 1 100.00
perf 1 1 100.00
uart_perf 360.980s 13954.456us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.470s 2639.732us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.470s 2639.732us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 16.310s 21036.239us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.200s 3603.988us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.280s 470.628us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.160s 3053.850us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 579.870s 90692.419us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 299.640s 141414.018us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.640s 15.010us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 13.297us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.790s 295.650us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.790s 295.650us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.880s 31.918us 1 1 100.00
uart_csr_rw 0.690s 12.878us 1 1 100.00
uart_csr_aliasing 0.710s 52.683us 1 1 100.00
uart_same_csr_outstanding 0.820s 53.660us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.880s 31.918us 1 1 100.00
uart_csr_rw 0.690s 12.878us 1 1 100.00
uart_csr_aliasing 0.710s 52.683us 1 1 100.00
uart_same_csr_outstanding 0.820s 53.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.770s 35.340us 1 1 100.00
uart_tl_intg_err 1.500s 179.965us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.500s 179.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 45.790s 4343.872us 1 1 100.00