Simulation Results: adc_ctrl

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.41 %
  • code
  • 93.79 %
  • assert
  • 92.54 %
  • func
  • 12.89 %
  • line
  • 98.68 %
  • branch
  • 97.15 %
  • cond
  • 86.85 %
  • toggle
  • 99.76 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.390s 5949.072us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.360s 1278.862us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.970s 385.989us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 2.520s 2386.451us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.990s 1073.605us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.940s 534.509us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.970s 385.989us 1 1 100.00
adc_ctrl_csr_aliasing 1.990s 1073.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.960s 525.410us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.050s 408.108us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.820s 291.853us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.030s 315.966us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.690s 425.774us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.350s 525.340us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.770s 287.460us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.920s 478.879us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.730s 4234.766us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 12.010s 25504.856us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 125.640s 82035.258us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 2.590s 1372.436us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.790s 338.521us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.320s 527.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.500s 373.873us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.500s 373.873us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.360s 1278.862us 1 1 100.00
adc_ctrl_csr_rw 0.970s 385.989us 1 1 100.00
adc_ctrl_csr_aliasing 1.990s 1073.605us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.670s 2463.020us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.360s 1278.862us 1 1 100.00
adc_ctrl_csr_rw 0.970s 385.989us 1 1 100.00
adc_ctrl_csr_aliasing 1.990s 1073.605us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.670s 2463.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.270s 8161.025us 1 1 100.00
adc_ctrl_tl_intg_err 13.020s 7811.667us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 13.020s 7811.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.150s 811.629us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 86725451161811249989243223554589581949608101858890915382115883531517459950871 386
UVM_INFO @ 525410300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 12471458742523556692253183164903922011022632792293056799309233458682850157920 386
UVM_INFO @ 408107854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 71085262397439054721633144584346150809424777537177369415234182790855120377729 386
UVM_INFO @ 291852836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 36378453328894705870989988425713418140665365511367634920614756868289715395288 386
UVM_INFO @ 315966140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 14295619965308468792431554897265225731755194680480540359126381695499805214213 386
UVM_INFO @ 425773939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 67857280464629823470819521946743358127994978946908755838574766901952167603414 386
UVM_INFO @ 525339528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 4993192703006491277702087159563200423250841887199726253571585937405869589553 386
UVM_INFO @ 478878938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 81013037506845441362364635502882545041616397928178411213414633729748903198808 386
UVM_INFO @ 287459511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 9887071206147542910733932498133839799745571105388240425933767643690260335160 392
UVM_INFO @ 811628992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 87487921763034217949701041657894585957655175042812082883939810710308544882871 397
UVM_INFO @ 1372435654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---