Simulation Results: aes/masked

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.66 %
  • code
  • 94.34 %
  • assert
  • 98.23 %
  • func
  • 73.42 %
  • block
  • 94.52 %
  • line
  • 96.03 %
  • branch
  • 87.79 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 100.856us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 71.129us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 92.952us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 104.140us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1793.047us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 207.582us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 88.757us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 104.140us 1 1 100.00
aes_csr_aliasing 3.000s 207.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 71.129us 1 1 100.00
aes_config_error 3.000s 66.360us 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 71.129us 1 1 100.00
aes_config_error 3.000s 66.360us 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 132.775us 1 1 100.00
aes_b2b 5.000s 679.213us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 71.129us 1 1 100.00
aes_config_error 3.000s 66.360us 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
aes_alert_reset 1.000s 32.989us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 72.943us 1 1 100.00
aes_config_error 3.000s 66.360us 1 1 100.00
aes_alert_reset 1.000s 32.989us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 69.472us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 719.927us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 1.000s 32.989us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 132.775us 1 1 100.00
aes_sideload 3.000s 132.033us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 527.009us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 9.000s 106.264us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 86.394us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 200.978us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 200.978us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 92.952us 1 1 100.00
aes_csr_rw 2.000s 104.140us 1 1 100.00
aes_csr_aliasing 3.000s 207.582us 1 1 100.00
aes_same_csr_outstanding 2.000s 165.150us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 92.952us 1 1 100.00
aes_csr_rw 2.000s 104.140us 1 1 100.00
aes_csr_aliasing 3.000s 207.582us 1 1 100.00
aes_same_csr_outstanding 2.000s 165.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 128.682us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 185.646us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 2910.561us 1 1 100.00
aes_tl_intg_err 2.000s 310.702us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 310.702us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 1.000s 32.989us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 71.129us 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
aes_alert_reset 1.000s 32.989us 0 1 0.00
aes_core_fi 2.000s 111.365us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 66.360us 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
aes_core_fi 2.000s 111.365us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 73.426us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 146.382us 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 132.775us 1 1 100.00
aes_sideload 3.000s 132.033us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 146.382us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 146.382us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 146.382us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 146.382us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 146.382us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 132.775us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 662.389us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
aes_ctr_fi 2.000s 107.972us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 662.389us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 662.389us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_ctr_fi 2.000s 107.972us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 662.389us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
aes_ctr_fi 2.000s 107.972us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 1.000s 32.989us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
aes_ctr_fi 2.000s 107.972us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
aes_ctr_fi 2.000s 107.972us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_ctr_fi 2.000s 107.972us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 662.389us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 662.389us 0 1 0.00
aes_control_fi 3.000s 285.724us 1 1 100.00
aes_cipher_fi 2.000s 53.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 9.000s 1182.381us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 111607358557982468028333021506739272460886103110195410408801681860852850958846 3302
UVM_INFO @ 106264333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 46510545433593463378270982656883874274252696542991397911007935638925225057430 383
UVM_INFO @ 1182380809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed 1 test run
aes_alert_reset 1890261418801335854490485379782766116474775001293363231554942575538291021889 1006
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 32989121 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 32989121 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 32989121 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 32989121 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 20979763721679345896289066558182929353750659207917215924155856473842014232028 8753
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0