Simulation Results: aes/unmasked

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.86 %
  • code
  • 88.99 %
  • assert
  • 97.92 %
  • func
  • 76.67 %
  • block
  • 89.38 %
  • line
  • 91.87 %
  • branch
  • 79.42 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 113.379us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 82.538us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 58.040us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 94.651us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 815.092us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 683.375us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 97.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 94.651us 1 1 100.00
aes_csr_aliasing 3.000s 683.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 82.538us 1 1 100.00
aes_config_error 2.000s 125.634us 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 82.538us 1 1 100.00
aes_config_error 2.000s 125.634us 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 176.413us 1 1 100.00
aes_b2b 5.000s 541.635us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 82.538us 1 1 100.00
aes_config_error 2.000s 125.634us 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
aes_alert_reset 2.000s 255.478us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 70.220us 1 1 100.00
aes_config_error 2.000s 125.634us 1 1 100.00
aes_alert_reset 2.000s 255.478us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 92.567us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 135.075us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 255.478us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 176.413us 1 1 100.00
aes_sideload 2.000s 57.103us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 59.646us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 17.000s 1099.944us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 60.568us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 75.080us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 75.080us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 58.040us 1 1 100.00
aes_csr_rw 1.000s 94.651us 1 1 100.00
aes_csr_aliasing 3.000s 683.375us 1 1 100.00
aes_same_csr_outstanding 2.000s 127.649us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 58.040us 1 1 100.00
aes_csr_rw 1.000s 94.651us 1 1 100.00
aes_csr_aliasing 3.000s 683.375us 1 1 100.00
aes_same_csr_outstanding 2.000s 127.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 472.049us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 81.392us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 862.813us 1 1 100.00
aes_tl_intg_err 3.000s 422.628us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 422.628us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 255.478us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 82.538us 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
aes_alert_reset 2.000s 255.478us 1 1 100.00
aes_core_fi 2.000s 70.280us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 125.634us 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
aes_core_fi 2.000s 70.280us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.687us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 56.477us 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 176.413us 1 1 100.00
aes_sideload 2.000s 57.103us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 56.477us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 56.477us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 56.477us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 56.477us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 56.477us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 176.413us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 84.966us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
aes_ctr_fi 3.000s 109.096us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 84.966us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 84.966us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_ctr_fi 3.000s 109.096us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 84.966us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
aes_ctr_fi 3.000s 109.096us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 255.478us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
aes_ctr_fi 3.000s 109.096us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
aes_ctr_fi 3.000s 109.096us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_ctr_fi 3.000s 109.096us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 84.966us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 84.966us 0 1 0.00
aes_control_fi 1.000s 87.471us 1 1 100.00
aes_cipher_fi 2.000s 57.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 50.591us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 105760820123928112847701184067302240884008170491442586859951048653810011114881 9403
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 19599966712345138889347361413495327474901915739697096879088292304903615195124 162
UVM_INFO @ 50591420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---