Simulation Results: alert_handler

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.64 %
  • code
  • 88.48 %
  • assert
  • 97.38 %
  • func
  • 80.05 %
  • line
  • 99.52 %
  • branch
  • 98.15 %
  • cond
  • 90.53 %
  • toggle
  • 92.90 %
  • FSM
  • 61.29 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 33.150s 1997.405us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.490s 22.184us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.440s 22.213us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 80.410s 6714.102us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 33.830s 571.701us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.330s 507.536us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.440s 22.213us 1 1 100.00
alert_handler_csr_aliasing 33.830s 571.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 57.790s 1340.089us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 25.550s 14055.040us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2528.140s 253307.120us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 13.040s 532.201us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 33.150s 1997.405us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 31.240s 1747.365us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 29.670s 860.787us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 285.130s 106683.910us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 601.200s 12002.141us 1 1 100.00
alert_handler_lpg_stub_clk 2122.180s 827833.282us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 730.820s 158488.155us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 7.280s 947.336us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.830s 214.430us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.680s 13.015us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.780s 231.097us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.780s 231.097us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.490s 22.184us 1 1 100.00
alert_handler_csr_rw 2.440s 22.213us 1 1 100.00
alert_handler_csr_aliasing 33.830s 571.701us 1 1 100.00
alert_handler_same_csr_outstanding 16.120s 3283.543us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.490s 22.184us 1 1 100.00
alert_handler_csr_rw 2.440s 22.213us 1 1 100.00
alert_handler_csr_aliasing 33.830s 571.701us 1 1 100.00
alert_handler_same_csr_outstanding 16.120s 3283.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 126.130s 3742.400us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 126.130s 3742.400us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 126.130s 3742.400us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 126.130s 3742.400us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 800.480s 57151.186us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
alert_handler_tl_intg_err 14.500s 237.367us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 14.500s 237.367us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 126.130s 3742.400us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 33.150s 1997.405us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 33.150s 1997.405us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 33.150s 1997.405us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 33.150s 1997.405us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.040s 532.201us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 601.200s 12002.141us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.040s 532.201us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2528.140s 253307.120us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2528.140s 253307.120us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.980s 942.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 54.820s 3066.175us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 22426418578406457070502104335689992130407589183767170049203321179909043242529 131
UVM_INFO @ 3066174979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---